1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 * Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_UTILITY_HH__
34#define __ARCH_ARM_UTILITY_HH__
35
36#include "arch/arm/miscregs.hh"
37#include "arch/arm/types.hh"
38#include "base/hashmap.hh"
39#include "base/types.hh"
40#include "cpu/thread_context.hh"
41
42namespace __hash_namespace {
43 template<>
44 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
45 size_t operator()(const ArmISA::ExtMachInst &emi) const {
46 return hash<uint32_t>::operator()((uint32_t)emi);
47 };
48 };
49}
50
51namespace ArmISA {
52
53 inline bool
54 testPredicate(CPSR cpsr, ConditionCode code)
55 {
56 switch (code)
57 {
58 case COND_EQ: return cpsr.z;
59 case COND_NE: return !cpsr.z;
60 case COND_CS: return cpsr.c;
61 case COND_CC: return !cpsr.c;
62 case COND_MI: return cpsr.n;
63 case COND_PL: return !cpsr.n;
64 case COND_VS: return cpsr.v;
65 case COND_VC: return !cpsr.v;
66 case COND_HI: return (cpsr.c && !cpsr.z);
67 case COND_LS: return !(cpsr.c && !cpsr.z);
68 case COND_GE: return !(cpsr.n ^ cpsr.v);
69 case COND_LT: return (cpsr.n ^ cpsr.v);
70 case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
71 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
72 case COND_AL: return true;
73 case COND_NV: return false;
74 default:
75 panic("Unhandled predicate condition: %d\n", code);
76 }
77 }
78
79 /**
80 * Function to insure ISA semantics about 0 registers.
81 * @param tc The thread context.
82 */
83 template <class TC>
84 void zeroRegisters(TC *tc);
85
86 // Instruction address compression hooks
87 static inline Addr realPCToFetchPC(const Addr &addr) {
88 return addr;
89 }
90
91 static inline Addr fetchPCToRealPC(const Addr &addr) {
92 return addr;
93 }
94
95 // the size of "fetched" instructions
96 static inline size_t fetchInstSize() {
97 return sizeof(MachInst);
98 }
99
100 static inline MachInst makeRegisterCopy(int dest, int src) {
101 panic("makeRegisterCopy not implemented");
102 return 0;
103 }
104
105 inline void startupCPU(ThreadContext *tc, int cpuId)
106 {
107 tc->activate(0);
108 }
109
110 template <class XC>
111 Fault
112 checkFpEnableFault(XC *xc)
113 {
114 return NoFault;
115 }
116
117 static inline void
118 copyRegs(ThreadContext *src, ThreadContext *dest)
119 {
120 panic("Copy Regs Not Implemented Yet\n");
121 }
122
123 static inline void
124 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
125 {
126 panic("Copy Misc. Regs Not Implemented Yet\n");
127 }
128
129 void initCPU(ThreadContext *tc, int cpuId);
130
131 static inline bool
132 inUserMode(ThreadContext *tc)
133 {
134 return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
135 }
136
137uint64_t getArgument(ThreadContext *tc, int number, bool fp);
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 * Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_UTILITY_HH__
34#define __ARCH_ARM_UTILITY_HH__
35
36#include "arch/arm/miscregs.hh"
37#include "arch/arm/types.hh"
38#include "base/hashmap.hh"
39#include "base/types.hh"
40#include "cpu/thread_context.hh"
41
42namespace __hash_namespace {
43 template<>
44 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
45 size_t operator()(const ArmISA::ExtMachInst &emi) const {
46 return hash<uint32_t>::operator()((uint32_t)emi);
47 };
48 };
49}
50
51namespace ArmISA {
52
53 inline bool
54 testPredicate(CPSR cpsr, ConditionCode code)
55 {
56 switch (code)
57 {
58 case COND_EQ: return cpsr.z;
59 case COND_NE: return !cpsr.z;
60 case COND_CS: return cpsr.c;
61 case COND_CC: return !cpsr.c;
62 case COND_MI: return cpsr.n;
63 case COND_PL: return !cpsr.n;
64 case COND_VS: return cpsr.v;
65 case COND_VC: return !cpsr.v;
66 case COND_HI: return (cpsr.c && !cpsr.z);
67 case COND_LS: return !(cpsr.c && !cpsr.z);
68 case COND_GE: return !(cpsr.n ^ cpsr.v);
69 case COND_LT: return (cpsr.n ^ cpsr.v);
70 case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
71 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
72 case COND_AL: return true;
73 case COND_NV: return false;
74 default:
75 panic("Unhandled predicate condition: %d\n", code);
76 }
77 }
78
79 /**
80 * Function to insure ISA semantics about 0 registers.
81 * @param tc The thread context.
82 */
83 template <class TC>
84 void zeroRegisters(TC *tc);
85
86 // Instruction address compression hooks
87 static inline Addr realPCToFetchPC(const Addr &addr) {
88 return addr;
89 }
90
91 static inline Addr fetchPCToRealPC(const Addr &addr) {
92 return addr;
93 }
94
95 // the size of "fetched" instructions
96 static inline size_t fetchInstSize() {
97 return sizeof(MachInst);
98 }
99
100 static inline MachInst makeRegisterCopy(int dest, int src) {
101 panic("makeRegisterCopy not implemented");
102 return 0;
103 }
104
105 inline void startupCPU(ThreadContext *tc, int cpuId)
106 {
107 tc->activate(0);
108 }
109
110 template <class XC>
111 Fault
112 checkFpEnableFault(XC *xc)
113 {
114 return NoFault;
115 }
116
117 static inline void
118 copyRegs(ThreadContext *src, ThreadContext *dest)
119 {
120 panic("Copy Regs Not Implemented Yet\n");
121 }
122
123 static inline void
124 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
125 {
126 panic("Copy Misc. Regs Not Implemented Yet\n");
127 }
128
129 void initCPU(ThreadContext *tc, int cpuId);
130
131 static inline bool
132 inUserMode(ThreadContext *tc)
133 {
134 return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
135 }
136
137uint64_t getArgument(ThreadContext *tc, int number, bool fp);
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