1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 * Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/logging.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
57class ArmSystem;
58
59namespace ArmISA {
60
61inline PCState
62buildRetPC(const PCState &curPC, const PCState &callPC)
63{
64 PCState retPC = callPC;
65 retPC.uEnd();
66 return retPC;
67}
68
69inline bool
70testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
71{
72 bool n = (nz & 0x2);
73 bool z = (nz & 0x1);
74
75 switch (code)
76 {
77 case COND_EQ: return z;
78 case COND_NE: return !z;
79 case COND_CS: return c;
80 case COND_CC: return !c;
81 case COND_MI: return n;
82 case COND_PL: return !n;
83 case COND_VS: return v;
84 case COND_VC: return !v;
85 case COND_HI: return (c && !z);
86 case COND_LS: return !(c && !z);
87 case COND_GE: return !(n ^ v);
88 case COND_LT: return (n ^ v);
89 case COND_GT: return !(n ^ v || z);
90 case COND_LE: return (n ^ v || z);
91 case COND_AL: return true;
92 case COND_UC: return true;
93 default:
94 panic("Unhandled predicate condition: %d\n", code);
95 }
96}
97
98/**
99 * Function to insure ISA semantics about 0 registers.
100 * @param tc The thread context.
101 */
102template <class TC>
103void zeroRegisters(TC *tc);
104
105inline void startupCPU(ThreadContext *tc, int cpuId)
106{
107 tc->activate();
108}
109
110void copyRegs(ThreadContext *src, ThreadContext *dest);
111
112static inline void
113copyMiscRegs(ThreadContext *src, ThreadContext *dest)
114{
115 panic("Copy Misc. Regs Not Implemented Yet\n");
116}
117
118void initCPU(ThreadContext *tc, int cpuId);
119
120static inline bool
121inUserMode(CPSR cpsr)
122{
123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
124}
125
126static inline bool
127inUserMode(ThreadContext *tc)
128{
129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
130}
131
132static inline bool
133inPrivilegedMode(CPSR cpsr)
134{
135 return !inUserMode(cpsr);
136}
137
138static inline bool
139inPrivilegedMode(ThreadContext *tc)
140{
141 return !inUserMode(tc);
142}
143
144bool inAArch64(ThreadContext *tc);
145
146static inline OperatingMode
147currOpMode(ThreadContext *tc)
148{
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
150 return (OperatingMode) (uint8_t) cpsr.mode;
151}
152
153static inline ExceptionLevel
154currEL(ThreadContext *tc)
155{
156 return opModeToEL(currOpMode(tc));
157}
158
| 1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 * Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/logging.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
57class ArmSystem;
58
59namespace ArmISA {
60
61inline PCState
62buildRetPC(const PCState &curPC, const PCState &callPC)
63{
64 PCState retPC = callPC;
65 retPC.uEnd();
66 return retPC;
67}
68
69inline bool
70testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
71{
72 bool n = (nz & 0x2);
73 bool z = (nz & 0x1);
74
75 switch (code)
76 {
77 case COND_EQ: return z;
78 case COND_NE: return !z;
79 case COND_CS: return c;
80 case COND_CC: return !c;
81 case COND_MI: return n;
82 case COND_PL: return !n;
83 case COND_VS: return v;
84 case COND_VC: return !v;
85 case COND_HI: return (c && !z);
86 case COND_LS: return !(c && !z);
87 case COND_GE: return !(n ^ v);
88 case COND_LT: return (n ^ v);
89 case COND_GT: return !(n ^ v || z);
90 case COND_LE: return (n ^ v || z);
91 case COND_AL: return true;
92 case COND_UC: return true;
93 default:
94 panic("Unhandled predicate condition: %d\n", code);
95 }
96}
97
98/**
99 * Function to insure ISA semantics about 0 registers.
100 * @param tc The thread context.
101 */
102template <class TC>
103void zeroRegisters(TC *tc);
104
105inline void startupCPU(ThreadContext *tc, int cpuId)
106{
107 tc->activate();
108}
109
110void copyRegs(ThreadContext *src, ThreadContext *dest);
111
112static inline void
113copyMiscRegs(ThreadContext *src, ThreadContext *dest)
114{
115 panic("Copy Misc. Regs Not Implemented Yet\n");
116}
117
118void initCPU(ThreadContext *tc, int cpuId);
119
120static inline bool
121inUserMode(CPSR cpsr)
122{
123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
124}
125
126static inline bool
127inUserMode(ThreadContext *tc)
128{
129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
130}
131
132static inline bool
133inPrivilegedMode(CPSR cpsr)
134{
135 return !inUserMode(cpsr);
136}
137
138static inline bool
139inPrivilegedMode(ThreadContext *tc)
140{
141 return !inUserMode(tc);
142}
143
144bool inAArch64(ThreadContext *tc);
145
146static inline OperatingMode
147currOpMode(ThreadContext *tc)
148{
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
150 return (OperatingMode) (uint8_t) cpsr.mode;
151}
152
153static inline ExceptionLevel
154currEL(ThreadContext *tc)
155{
156 return opModeToEL(currOpMode(tc));
157}
158
|
159/**
160 * This function checks whether selected EL provided as an argument
161 * is using the AArch32 ISA. This information might be unavailable
162 * at the current EL status: it hence returns a pair of boolean values:
163 * a first boolean, true if information is available (known),
164 * and a second one, true if EL is using AArch32, false for AArch64.
165 *
166 * @param tc The thread context.
167 * @param el The target exception level.
168 * @retval known is FALSE for EL0 if the current Exception level
169 * is not EL0 and EL1 is using AArch64, since it cannot
170 * determine the state of EL0; TRUE otherwise.
171 * @retval aarch32 is TRUE if the specified Exception level is using AArch32;
172 * FALSE otherwise.
173 */
174std::pair<bool, bool>
175ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el);
176
177bool ELIs32(ThreadContext *tc, ExceptionLevel el);
178
179bool ELIs64(ThreadContext *tc, ExceptionLevel el);
180
181/**
182 * Returns true if the current exception level `el` is executing a Host OS or
183 * an application of a Host OS (Armv8.1 Virtualization Host Extensions).
184 */
185bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
186
187bool isBigEndian64(ThreadContext *tc);
188
189/**
190 * badMode is checking if the execution mode provided as an argument is
191 * valid and implemented for AArch32
192 *
193 * @param tc ThreadContext
194 * @param mode OperatingMode to check
195 * @return false if mode is valid and implemented, true otherwise
196 */
197bool badMode32(ThreadContext *tc, OperatingMode mode);
198
199/**
200 * badMode is checking if the execution mode provided as an argument is
201 * valid and implemented.
202 *
203 * @param tc ThreadContext
204 * @param mode OperatingMode to check
205 * @return false if mode is valid and implemented, true otherwise
206 */
207bool badMode(ThreadContext *tc, OperatingMode mode);
208
209static inline uint8_t
210itState(CPSR psr)
211{
212 ITSTATE it = 0;
213 it.top6 = psr.it2;
214 it.bottom2 = psr.it1;
215
216 return (uint8_t)it;
217}
218
219/**
220 * Removes the tag from tagged addresses if that mode is enabled.
221 * @param addr The address to be purified.
222 * @param tc The thread context.
223 * @param el The controlled exception level.
224 * @return The purified address.
225 */
226Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
227 TTBCR tcr);
228Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
229
230static inline bool
231inSecureState(SCR scr, CPSR cpsr)
232{
233 switch ((OperatingMode) (uint8_t) cpsr.mode) {
234 case MODE_MON:
235 case MODE_EL3T:
236 case MODE_EL3H:
237 return true;
238 case MODE_HYP:
239 case MODE_EL2T:
240 case MODE_EL2H:
241 return false;
242 default:
243 return !scr.ns;
244 }
245}
246
247bool inSecureState(ThreadContext *tc);
248
249/**
250 * Return TRUE if an Exception level below EL3 is in Secure state.
251 * Differs from inSecureState in that it ignores the current EL
252 * or Mode in considering security state.
253 */
254inline bool isSecureBelowEL3(ThreadContext *tc);
255
256bool longDescFormatInUse(ThreadContext *tc);
257
258/** This helper function is either returing the value of
259 * MPIDR_EL1 (by calling getMPIDR), or it is issuing a read
260 * to VMPIDR_EL2 (as it happens in virtualized systems) */
261RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
262
263/** This helper function is returing the value of MPIDR_EL1 */
264RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
265
266static inline uint32_t
267mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
268 uint32_t opc1, uint32_t opc2)
269{
270 return (isRead << 0) |
271 (crm << 1) |
272 (rt << 5) |
273 (crn << 10) |
274 (opc1 << 14) |
275 (opc2 << 17);
276}
277
278static inline void
279mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
280 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
281{
282 isRead = (iss >> 0) & 0x1;
283 crm = (iss >> 1) & 0xF;
284 rt = (IntRegIndex) ((iss >> 5) & 0xF);
285 crn = (iss >> 10) & 0xF;
286 opc1 = (iss >> 14) & 0x7;
287 opc2 = (iss >> 17) & 0x7;
288}
289
290static inline uint32_t
291mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
292 uint32_t opc1)
293{
294 return (isRead << 0) |
295 (crm << 1) |
296 (rt << 5) |
297 (rt2 << 10) |
298 (opc1 << 16);
299}
300
301static inline uint32_t
302msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
303 uint32_t crm, uint32_t op2, IntRegIndex rt)
304{
305 return isRead |
306 (crm << 1) |
307 (rt << 5) |
308 (crn << 10) |
309 (op1 << 14) |
310 (op2 << 17) |
311 (op0 << 20);
312}
313
314bool
315mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss);
316
317bool
318mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
319 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
320bool
321mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
322 HCR hcr, uint32_t iss);
323
324bool SPAlignmentCheckEnabled(ThreadContext* tc);
325
326uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
327
328void skipFunction(ThreadContext *tc);
329
330inline void
331advancePC(PCState &pc, const StaticInstPtr &inst)
332{
333 inst->advancePC(pc);
334}
335
336Addr truncPage(Addr addr);
337Addr roundPage(Addr addr);
338
339inline uint64_t
340getExecutingAsid(ThreadContext *tc)
341{
342 return tc->readMiscReg(MISCREG_CONTEXTIDR);
343}
344
345// Decodes the register index to access based on the fields used in a MSR
346// or MRS instruction
347bool
348decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
349 CPSR cpsr, SCR scr, NSACR nsacr,
350 bool checkSecurity = true);
351
352// This wrapper function is used to turn the register index into a source
353// parameter for the instruction. See Operands.isa
354static inline int
355decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
356{
357 int regIdx;
358 bool isIntReg;
359 bool validReg;
360
361 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
362 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
363}
364
365/**
366 * Returns the n. of PA bits corresponding to the specified encoding.
367 */
368int decodePhysAddrRange64(uint8_t pa_enc);
369
370/**
371 * Returns the encoding corresponding to the specified n. of PA bits.
372 */
373uint8_t encodePhysAddrRange64(int pa_size);
374
375inline ByteOrder byteOrder(ThreadContext *tc)
376{
377 return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
378};
379
380}
381
382#endif
| 165/**
166 * This function checks whether selected EL provided as an argument
167 * is using the AArch32 ISA. This information might be unavailable
168 * at the current EL status: it hence returns a pair of boolean values:
169 * a first boolean, true if information is available (known),
170 * and a second one, true if EL is using AArch32, false for AArch64.
171 *
172 * @param tc The thread context.
173 * @param el The target exception level.
174 * @retval known is FALSE for EL0 if the current Exception level
175 * is not EL0 and EL1 is using AArch64, since it cannot
176 * determine the state of EL0; TRUE otherwise.
177 * @retval aarch32 is TRUE if the specified Exception level is using AArch32;
178 * FALSE otherwise.
179 */
180std::pair<bool, bool>
181ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el);
182
183bool ELIs32(ThreadContext *tc, ExceptionLevel el);
184
185bool ELIs64(ThreadContext *tc, ExceptionLevel el);
186
187/**
188 * Returns true if the current exception level `el` is executing a Host OS or
189 * an application of a Host OS (Armv8.1 Virtualization Host Extensions).
190 */
191bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
192
193bool isBigEndian64(ThreadContext *tc);
194
195/**
196 * badMode is checking if the execution mode provided as an argument is
197 * valid and implemented for AArch32
198 *
199 * @param tc ThreadContext
200 * @param mode OperatingMode to check
201 * @return false if mode is valid and implemented, true otherwise
202 */
203bool badMode32(ThreadContext *tc, OperatingMode mode);
204
205/**
206 * badMode is checking if the execution mode provided as an argument is
207 * valid and implemented.
208 *
209 * @param tc ThreadContext
210 * @param mode OperatingMode to check
211 * @return false if mode is valid and implemented, true otherwise
212 */
213bool badMode(ThreadContext *tc, OperatingMode mode);
214
215static inline uint8_t
216itState(CPSR psr)
217{
218 ITSTATE it = 0;
219 it.top6 = psr.it2;
220 it.bottom2 = psr.it1;
221
222 return (uint8_t)it;
223}
224
225/**
226 * Removes the tag from tagged addresses if that mode is enabled.
227 * @param addr The address to be purified.
228 * @param tc The thread context.
229 * @param el The controlled exception level.
230 * @return The purified address.
231 */
232Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
233 TTBCR tcr);
234Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
235
236static inline bool
237inSecureState(SCR scr, CPSR cpsr)
238{
239 switch ((OperatingMode) (uint8_t) cpsr.mode) {
240 case MODE_MON:
241 case MODE_EL3T:
242 case MODE_EL3H:
243 return true;
244 case MODE_HYP:
245 case MODE_EL2T:
246 case MODE_EL2H:
247 return false;
248 default:
249 return !scr.ns;
250 }
251}
252
253bool inSecureState(ThreadContext *tc);
254
255/**
256 * Return TRUE if an Exception level below EL3 is in Secure state.
257 * Differs from inSecureState in that it ignores the current EL
258 * or Mode in considering security state.
259 */
260inline bool isSecureBelowEL3(ThreadContext *tc);
261
262bool longDescFormatInUse(ThreadContext *tc);
263
264/** This helper function is either returing the value of
265 * MPIDR_EL1 (by calling getMPIDR), or it is issuing a read
266 * to VMPIDR_EL2 (as it happens in virtualized systems) */
267RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
268
269/** This helper function is returing the value of MPIDR_EL1 */
270RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
271
272static inline uint32_t
273mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
274 uint32_t opc1, uint32_t opc2)
275{
276 return (isRead << 0) |
277 (crm << 1) |
278 (rt << 5) |
279 (crn << 10) |
280 (opc1 << 14) |
281 (opc2 << 17);
282}
283
284static inline void
285mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
286 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
287{
288 isRead = (iss >> 0) & 0x1;
289 crm = (iss >> 1) & 0xF;
290 rt = (IntRegIndex) ((iss >> 5) & 0xF);
291 crn = (iss >> 10) & 0xF;
292 opc1 = (iss >> 14) & 0x7;
293 opc2 = (iss >> 17) & 0x7;
294}
295
296static inline uint32_t
297mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
298 uint32_t opc1)
299{
300 return (isRead << 0) |
301 (crm << 1) |
302 (rt << 5) |
303 (rt2 << 10) |
304 (opc1 << 16);
305}
306
307static inline uint32_t
308msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
309 uint32_t crm, uint32_t op2, IntRegIndex rt)
310{
311 return isRead |
312 (crm << 1) |
313 (rt << 5) |
314 (crn << 10) |
315 (op1 << 14) |
316 (op2 << 17) |
317 (op0 << 20);
318}
319
320bool
321mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss);
322
323bool
324mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
325 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
326bool
327mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
328 HCR hcr, uint32_t iss);
329
330bool SPAlignmentCheckEnabled(ThreadContext* tc);
331
332uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
333
334void skipFunction(ThreadContext *tc);
335
336inline void
337advancePC(PCState &pc, const StaticInstPtr &inst)
338{
339 inst->advancePC(pc);
340}
341
342Addr truncPage(Addr addr);
343Addr roundPage(Addr addr);
344
345inline uint64_t
346getExecutingAsid(ThreadContext *tc)
347{
348 return tc->readMiscReg(MISCREG_CONTEXTIDR);
349}
350
351// Decodes the register index to access based on the fields used in a MSR
352// or MRS instruction
353bool
354decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
355 CPSR cpsr, SCR scr, NSACR nsacr,
356 bool checkSecurity = true);
357
358// This wrapper function is used to turn the register index into a source
359// parameter for the instruction. See Operands.isa
360static inline int
361decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
362{
363 int regIdx;
364 bool isIntReg;
365 bool validReg;
366
367 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
368 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
369}
370
371/**
372 * Returns the n. of PA bits corresponding to the specified encoding.
373 */
374int decodePhysAddrRange64(uint8_t pa_enc);
375
376/**
377 * Returns the encoding corresponding to the specified n. of PA bits.
378 */
379uint8_t encodePhysAddrRange64(int pa_size);
380
381inline ByteOrder byteOrder(ThreadContext *tc)
382{
383 return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
384};
385
386}
387
388#endif
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