1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 * Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/logging.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
57class ArmSystem;
58
59namespace ArmISA {
60
61inline PCState
62buildRetPC(const PCState &curPC, const PCState &callPC)
63{
64 PCState retPC = callPC;
65 retPC.uEnd();
66 return retPC;
67}
68
69inline bool
70testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
71{
72 bool n = (nz & 0x2);
73 bool z = (nz & 0x1);
74
75 switch (code)
76 {
77 case COND_EQ: return z;
78 case COND_NE: return !z;
79 case COND_CS: return c;
80 case COND_CC: return !c;
81 case COND_MI: return n;
82 case COND_PL: return !n;
83 case COND_VS: return v;
84 case COND_VC: return !v;
85 case COND_HI: return (c && !z);
86 case COND_LS: return !(c && !z);
87 case COND_GE: return !(n ^ v);
88 case COND_LT: return (n ^ v);
89 case COND_GT: return !(n ^ v || z);
90 case COND_LE: return (n ^ v || z);
91 case COND_AL: return true;
92 case COND_UC: return true;
93 default:
94 panic("Unhandled predicate condition: %d\n", code);
95 }
96}
97
98/**
99 * Function to insure ISA semantics about 0 registers.
100 * @param tc The thread context.
101 */
102template <class TC>
103void zeroRegisters(TC *tc);
104
105inline void startupCPU(ThreadContext *tc, int cpuId)
106{
107 tc->activate();
108}
109
110void copyRegs(ThreadContext *src, ThreadContext *dest);
111
112static inline void
113copyMiscRegs(ThreadContext *src, ThreadContext *dest)
114{
115 panic("Copy Misc. Regs Not Implemented Yet\n");
116}
117
118void initCPU(ThreadContext *tc, int cpuId);
119
120static inline bool
121inUserMode(CPSR cpsr)
122{
123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
124}
125
126static inline bool
127inUserMode(ThreadContext *tc)
128{
129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
130}
131
132static inline bool
133inPrivilegedMode(CPSR cpsr)
134{
135 return !inUserMode(cpsr);
136}
137
138static inline bool
139inPrivilegedMode(ThreadContext *tc)
140{
141 return !inUserMode(tc);
142}
143
144bool inAArch64(ThreadContext *tc);
145
146static inline OperatingMode
147currOpMode(ThreadContext *tc)
148{
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
150 return (OperatingMode) (uint8_t) cpsr.mode;
151}
152
153static inline ExceptionLevel
154currEL(ThreadContext *tc)
155{
156 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
157 return (ExceptionLevel) (uint8_t) cpsr.el;
158}
159
| 1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 * Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/logging.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
57class ArmSystem;
58
59namespace ArmISA {
60
61inline PCState
62buildRetPC(const PCState &curPC, const PCState &callPC)
63{
64 PCState retPC = callPC;
65 retPC.uEnd();
66 return retPC;
67}
68
69inline bool
70testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
71{
72 bool n = (nz & 0x2);
73 bool z = (nz & 0x1);
74
75 switch (code)
76 {
77 case COND_EQ: return z;
78 case COND_NE: return !z;
79 case COND_CS: return c;
80 case COND_CC: return !c;
81 case COND_MI: return n;
82 case COND_PL: return !n;
83 case COND_VS: return v;
84 case COND_VC: return !v;
85 case COND_HI: return (c && !z);
86 case COND_LS: return !(c && !z);
87 case COND_GE: return !(n ^ v);
88 case COND_LT: return (n ^ v);
89 case COND_GT: return !(n ^ v || z);
90 case COND_LE: return (n ^ v || z);
91 case COND_AL: return true;
92 case COND_UC: return true;
93 default:
94 panic("Unhandled predicate condition: %d\n", code);
95 }
96}
97
98/**
99 * Function to insure ISA semantics about 0 registers.
100 * @param tc The thread context.
101 */
102template <class TC>
103void zeroRegisters(TC *tc);
104
105inline void startupCPU(ThreadContext *tc, int cpuId)
106{
107 tc->activate();
108}
109
110void copyRegs(ThreadContext *src, ThreadContext *dest);
111
112static inline void
113copyMiscRegs(ThreadContext *src, ThreadContext *dest)
114{
115 panic("Copy Misc. Regs Not Implemented Yet\n");
116}
117
118void initCPU(ThreadContext *tc, int cpuId);
119
120static inline bool
121inUserMode(CPSR cpsr)
122{
123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
124}
125
126static inline bool
127inUserMode(ThreadContext *tc)
128{
129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
130}
131
132static inline bool
133inPrivilegedMode(CPSR cpsr)
134{
135 return !inUserMode(cpsr);
136}
137
138static inline bool
139inPrivilegedMode(ThreadContext *tc)
140{
141 return !inUserMode(tc);
142}
143
144bool inAArch64(ThreadContext *tc);
145
146static inline OperatingMode
147currOpMode(ThreadContext *tc)
148{
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
150 return (OperatingMode) (uint8_t) cpsr.mode;
151}
152
153static inline ExceptionLevel
154currEL(ThreadContext *tc)
155{
156 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
157 return (ExceptionLevel) (uint8_t) cpsr.el;
158}
159
|
160bool ELIs32(ThreadContext *tc, ExceptionLevel el);
161
162bool ELIs64(ThreadContext *tc, ExceptionLevel el);
163
164bool isBigEndian64(ThreadContext *tc);
165
166static inline uint8_t
167itState(CPSR psr)
168{
169 ITSTATE it = 0;
170 it.top6 = psr.it2;
171 it.bottom2 = psr.it1;
172
173 return (uint8_t)it;
174}
175
176/**
177 * Removes the tag from tagged addresses if that mode is enabled.
178 * @param addr The address to be purified.
179 * @param tc The thread context.
180 * @param el The controlled exception level.
181 * @return The purified address.
182 */
183Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
184 TTBCR tcr);
185Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
186
187static inline bool
188inSecureState(SCR scr, CPSR cpsr)
189{
190 switch ((OperatingMode) (uint8_t) cpsr.mode) {
191 case MODE_MON:
192 case MODE_EL3T:
193 case MODE_EL3H:
194 return true;
195 case MODE_HYP:
196 case MODE_EL2T:
197 case MODE_EL2H:
198 return false;
199 default:
200 return !scr.ns;
201 }
202}
203
204bool inSecureState(ThreadContext *tc);
205
206/**
207 * Return TRUE if an Exception level below EL3 is in Secure state.
208 * Differs from inSecureState in that it ignores the current EL
209 * or Mode in considering security state.
210 */
211inline bool isSecureBelowEL3(ThreadContext *tc);
212
213bool longDescFormatInUse(ThreadContext *tc);
214
215uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
216
217static inline uint32_t
218mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
219 uint32_t opc1, uint32_t opc2)
220{
221 return (isRead << 0) |
222 (crm << 1) |
223 (rt << 5) |
224 (crn << 10) |
225 (opc1 << 14) |
226 (opc2 << 17);
227}
228
229static inline void
230mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
231 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
232{
233 isRead = (iss >> 0) & 0x1;
234 crm = (iss >> 1) & 0xF;
235 rt = (IntRegIndex) ((iss >> 5) & 0xF);
236 crn = (iss >> 10) & 0xF;
237 opc1 = (iss >> 14) & 0x7;
238 opc2 = (iss >> 17) & 0x7;
239}
240
241static inline uint32_t
242mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
243 uint32_t opc1)
244{
245 return (isRead << 0) |
246 (crm << 1) |
247 (rt << 5) |
248 (rt2 << 10) |
249 (opc1 << 16);
250}
251
252static inline uint32_t
253msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
254 uint32_t crm, uint32_t op2, IntRegIndex rt)
255{
256 return isRead |
257 (crm << 1) |
258 (rt << 5) |
259 (crn << 10) |
260 (op1 << 14) |
261 (op2 << 17) |
262 (op0 << 20);
263}
264
265bool
266mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
267 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
268bool
269mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
270 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
271bool
272mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
273 HCR hcr, uint32_t iss);
274
275bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
276 CPACR cpacr);
277bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, ExceptionLevel el,
278 bool isRead, CPTR cptr, HCR hcr, bool * isVfpNeon);
279bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr,
280 ExceptionLevel el, bool * isVfpNeon);
281
282bool SPAlignmentCheckEnabled(ThreadContext* tc);
283
284uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
285
286void skipFunction(ThreadContext *tc);
287
288inline void
289advancePC(PCState &pc, const StaticInstPtr &inst)
290{
291 inst->advancePC(pc);
292}
293
294Addr truncPage(Addr addr);
295Addr roundPage(Addr addr);
296
297inline uint64_t
298getExecutingAsid(ThreadContext *tc)
299{
300 return tc->readMiscReg(MISCREG_CONTEXTIDR);
301}
302
303// Decodes the register index to access based on the fields used in a MSR
304// or MRS instruction
305bool
306decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
307 CPSR cpsr, SCR scr, NSACR nsacr,
308 bool checkSecurity = true);
309
310// This wrapper function is used to turn the register index into a source
311// parameter for the instruction. See Operands.isa
312static inline int
313decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
314{
315 int regIdx;
316 bool isIntReg;
317 bool validReg;
318
319 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
320 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
321}
322
323/**
324 * Returns the n. of PA bits corresponding to the specified encoding.
325 */
326int decodePhysAddrRange64(uint8_t pa_enc);
327
328/**
329 * Returns the encoding corresponding to the specified n. of PA bits.
330 */
331uint8_t encodePhysAddrRange64(int pa_size);
332
333}
334
335#endif
| 178bool ELIs32(ThreadContext *tc, ExceptionLevel el);
179
180bool ELIs64(ThreadContext *tc, ExceptionLevel el);
181
182bool isBigEndian64(ThreadContext *tc);
183
184static inline uint8_t
185itState(CPSR psr)
186{
187 ITSTATE it = 0;
188 it.top6 = psr.it2;
189 it.bottom2 = psr.it1;
190
191 return (uint8_t)it;
192}
193
194/**
195 * Removes the tag from tagged addresses if that mode is enabled.
196 * @param addr The address to be purified.
197 * @param tc The thread context.
198 * @param el The controlled exception level.
199 * @return The purified address.
200 */
201Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
202 TTBCR tcr);
203Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
204
205static inline bool
206inSecureState(SCR scr, CPSR cpsr)
207{
208 switch ((OperatingMode) (uint8_t) cpsr.mode) {
209 case MODE_MON:
210 case MODE_EL3T:
211 case MODE_EL3H:
212 return true;
213 case MODE_HYP:
214 case MODE_EL2T:
215 case MODE_EL2H:
216 return false;
217 default:
218 return !scr.ns;
219 }
220}
221
222bool inSecureState(ThreadContext *tc);
223
224/**
225 * Return TRUE if an Exception level below EL3 is in Secure state.
226 * Differs from inSecureState in that it ignores the current EL
227 * or Mode in considering security state.
228 */
229inline bool isSecureBelowEL3(ThreadContext *tc);
230
231bool longDescFormatInUse(ThreadContext *tc);
232
233uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
234
235static inline uint32_t
236mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
237 uint32_t opc1, uint32_t opc2)
238{
239 return (isRead << 0) |
240 (crm << 1) |
241 (rt << 5) |
242 (crn << 10) |
243 (opc1 << 14) |
244 (opc2 << 17);
245}
246
247static inline void
248mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
249 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
250{
251 isRead = (iss >> 0) & 0x1;
252 crm = (iss >> 1) & 0xF;
253 rt = (IntRegIndex) ((iss >> 5) & 0xF);
254 crn = (iss >> 10) & 0xF;
255 opc1 = (iss >> 14) & 0x7;
256 opc2 = (iss >> 17) & 0x7;
257}
258
259static inline uint32_t
260mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
261 uint32_t opc1)
262{
263 return (isRead << 0) |
264 (crm << 1) |
265 (rt << 5) |
266 (rt2 << 10) |
267 (opc1 << 16);
268}
269
270static inline uint32_t
271msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
272 uint32_t crm, uint32_t op2, IntRegIndex rt)
273{
274 return isRead |
275 (crm << 1) |
276 (rt << 5) |
277 (crn << 10) |
278 (op1 << 14) |
279 (op2 << 17) |
280 (op0 << 20);
281}
282
283bool
284mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
285 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
286bool
287mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
288 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
289bool
290mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
291 HCR hcr, uint32_t iss);
292
293bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
294 CPACR cpacr);
295bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, ExceptionLevel el,
296 bool isRead, CPTR cptr, HCR hcr, bool * isVfpNeon);
297bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr,
298 ExceptionLevel el, bool * isVfpNeon);
299
300bool SPAlignmentCheckEnabled(ThreadContext* tc);
301
302uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
303
304void skipFunction(ThreadContext *tc);
305
306inline void
307advancePC(PCState &pc, const StaticInstPtr &inst)
308{
309 inst->advancePC(pc);
310}
311
312Addr truncPage(Addr addr);
313Addr roundPage(Addr addr);
314
315inline uint64_t
316getExecutingAsid(ThreadContext *tc)
317{
318 return tc->readMiscReg(MISCREG_CONTEXTIDR);
319}
320
321// Decodes the register index to access based on the fields used in a MSR
322// or MRS instruction
323bool
324decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
325 CPSR cpsr, SCR scr, NSACR nsacr,
326 bool checkSecurity = true);
327
328// This wrapper function is used to turn the register index into a source
329// parameter for the instruction. See Operands.isa
330static inline int
331decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
332{
333 int regIdx;
334 bool isIntReg;
335 bool validReg;
336
337 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
338 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
339}
340
341/**
342 * Returns the n. of PA bits corresponding to the specified encoding.
343 */
344int decodePhysAddrRange64(uint8_t pa_enc);
345
346/**
347 * Returns the encoding corresponding to the specified n. of PA bits.
348 */
349uint8_t encodePhysAddrRange64(int pa_size);
350
351}
352
353#endif
|