1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51#include "base/misc.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
57namespace ArmISA {
58
59 inline PCState
60 buildRetPC(const PCState &curPC, const PCState &callPC)
61 {
62 PCState retPC = callPC;
63 retPC.uEnd();
64 return retPC;
65 }
66
67 inline bool
68 testPredicate(CPSR cpsr, ConditionCode code)
69 {
70 switch (code)
71 {
72 case COND_EQ: return cpsr.z;
73 case COND_NE: return !cpsr.z;
74 case COND_CS: return cpsr.c;
75 case COND_CC: return !cpsr.c;
76 case COND_MI: return cpsr.n;
77 case COND_PL: return !cpsr.n;
78 case COND_VS: return cpsr.v;
79 case COND_VC: return !cpsr.v;
80 case COND_HI: return (cpsr.c && !cpsr.z);
81 case COND_LS: return !(cpsr.c && !cpsr.z);
82 case COND_GE: return !(cpsr.n ^ cpsr.v);
83 case COND_LT: return (cpsr.n ^ cpsr.v);
84 case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
85 case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
86 case COND_AL: return true;
87 case COND_UC: return true;
88 default:
89 panic("Unhandled predicate condition: %d\n", code);
90 }
91 }
92
93 /**
94 * Function to insure ISA semantics about 0 registers.
95 * @param tc The thread context.
96 */
97 template <class TC>
98 void zeroRegisters(TC *tc);
99
100 inline void startupCPU(ThreadContext *tc, int cpuId)
101 {
102 tc->activate(0);
103 }
104
105 void copyRegs(ThreadContext *src, ThreadContext *dest);
106
107 static inline void
108 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
109 {
110 panic("Copy Misc. Regs Not Implemented Yet\n");
111 }
112
113 void initCPU(ThreadContext *tc, int cpuId);
114
115 static inline bool
116 inUserMode(CPSR cpsr)
117 {
118 return cpsr.mode == MODE_USER;
119 }
120
121 static inline bool
122 inUserMode(ThreadContext *tc)
123 {
124 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
125 }
126
127 static inline bool
128 inPrivilegedMode(CPSR cpsr)
129 {
130 return !inUserMode(cpsr);
131 }
132
133 static inline bool
134 inPrivilegedMode(ThreadContext *tc)
135 {
136 return !inUserMode(tc);
137 }
138
139 static inline bool
140 vfpEnabled(CPACR cpacr, CPSR cpsr)
141 {
142 return cpacr.cp10 == 0x3 ||
143 (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
144 }
145
146 static inline bool
147 vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
148 {
149 return fpexc.en && vfpEnabled(cpacr, cpsr);
150 }
151
152 static inline bool
153 neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
154 {
155 return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
156 }
157
158uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
159
160Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
161Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
162
163void skipFunction(ThreadContext *tc);
164
165inline void
166advancePC(PCState &pc, const StaticInstPtr inst)
167{
168 inst->advancePC(pc);
169}
170
171};
172
173
174#endif