1/*
2 * Copyright (c) 2010, 2012-2013, 2015,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#include "arch/arm/system.hh"
44
45#include <iostream>
46
47#include "arch/arm/semihosting.hh"
48#include "base/loader/object_file.hh"
49#include "base/loader/symtab.hh"
50#include "cpu/thread_context.hh"
51#include "mem/fs_translating_port_proxy.hh"
52#include "mem/physical.hh"
53#include "sim/full_system.hh"
54
55using namespace std;
56using namespace Linux;
57
58ArmSystem::ArmSystem(Params *p)
59 : System(p),
60 bootLoaders(), bootldr(nullptr),
61 _haveSecurity(p->have_security),
62 _haveLPAE(p->have_lpae),
63 _haveVirtualization(p->have_virtualization),
|
65 _genericTimer(nullptr),
66 _highestELIs64(p->highest_el_is_64),
67 _resetAddr64(p->auto_reset_addr_64 ?
68 (kernelEntry & loadAddrMask) + loadAddrOffset :
69 p->reset_addr_64),
70 _physAddrRange64(p->phys_addr_range_64),
71 _haveLargeAsid64(p->have_large_asid_64),
72 _m5opRange(p->m5ops_base ?
73 RangeSize(p->m5ops_base, 0x10000) :
74 AddrRange(1, 0)), // Create an empty range if disabled
75 semihosting(p->semihosting),
76 multiProc(p->multi_proc)
77{
78 // Check if the physical address range is valid
79 if (_highestELIs64 && (
80 _physAddrRange64 < 32 ||
81 _physAddrRange64 > 48 ||
82 (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
83 fatal("Invalid physical address range (%d)\n", _physAddrRange64);
84 }
85
86 bootLoaders.reserve(p->boot_loader.size());
87 for (const auto &bl : p->boot_loader) {
88 std::unique_ptr<ObjectFile> obj;
89 obj.reset(createObjectFile(bl));
90
91 fatal_if(!obj, "Could not read bootloader: %s\n", bl);
92 bootLoaders.emplace_back(std::move(obj));
93 }
94
95 if (kernel) {
96 bootldr = getBootLoader(kernel);
97 } else if (!bootLoaders.empty()) {
98 // No kernel specified, default to the first boot loader
99 bootldr = bootLoaders[0].get();
100 }
101
102 if (!bootLoaders.empty() && !bootldr)
103 fatal("Can't find a matching boot loader / kernel combination!");
104
105 if (bootldr) {
106 bootldr->loadGlobalSymbols(debugSymbolTable);
107 if ((bootldr->getArch() == ObjectFile::Arm64) && !_highestELIs64) {
108 warn("Highest ARM exception-level set to AArch32 but bootloader "
109 "is for AArch64. Assuming you wanted these to match.\n");
110 _highestELIs64 = true;
111 } else if ((bootldr->getArch() == ObjectFile::Arm) && _highestELIs64) {
112 warn("Highest ARM exception-level set to AArch64 but bootloader "
113 "is for AArch32. Assuming you wanted these to match.\n");
114 _highestELIs64 = false;
115 }
116 }
117
118 debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
119}
120
121void
122ArmSystem::initState()
123{
124 // Moved from the constructor to here since it relies on the
125 // address map being resolved in the interconnect
126
127 // Call the initialisation of the super class
128 System::initState();
129
130 const Params* p = params();
131
132 if (bootldr) {
133 bootldr->loadSections(physProxy);
134
135 uint8_t jump_to_bl_32[] =
136 {
137 0x07, 0xf0, 0xa0, 0xe1 // branch to r7 in aarch32
138 };
139
140 uint8_t jump_to_bl_64[] =
141 {
142 0xe0, 0x00, 0x1f, 0xd6 // instruction "br x7" in aarch64
143 };
144
145 // write the jump to branch table into address 0
146 if (!_highestELIs64)
147 physProxy.writeBlob(0x0, jump_to_bl_32, sizeof(jump_to_bl_32));
148 else
149 physProxy.writeBlob(0x0, jump_to_bl_64, sizeof(jump_to_bl_64));
150
151 inform("Using bootloader at address %#x\n", bootldr->entryPoint());
152
153 // Put the address of the boot loader into r7 so we know
154 // where to branch to after the reset fault
155 // All other values needed by the boot loader to know what to do
156 if (!p->gic_cpu_addr || !p->flags_addr)
157 fatal("gic_cpu_addr && flags_addr must be set with bootloader\n");
158
159 for (int i = 0; i < threadContexts.size(); i++) {
160 if (!_highestELIs64)
161 threadContexts[i]->setIntReg(3, (kernelEntry & loadAddrMask) +
162 loadAddrOffset);
163 threadContexts[i]->setIntReg(4, params()->gic_cpu_addr);
164 threadContexts[i]->setIntReg(5, params()->flags_addr);
165 threadContexts[i]->setIntReg(7, bootldr->entryPoint());
166 }
167 inform("Using kernel entry physical address at %#x\n",
168 (kernelEntry & loadAddrMask) + loadAddrOffset);
169 } else {
170 // Set the initial PC to be at start of the kernel code
171 if (!_highestELIs64)
172 threadContexts[0]->pcState((kernelEntry & loadAddrMask) +
173 loadAddrOffset);
174 }
175}
176
177ArmSystem*
178ArmSystem::getArmSystem(ThreadContext *tc)
179{
180 ArmSystem *a_sys = dynamic_cast<ArmSystem *>(tc->getSystemPtr());
181 assert(a_sys);
182 return a_sys;
183}
184
185bool
186ArmSystem::haveSecurity(ThreadContext *tc)
187{
188 return FullSystem? getArmSystem(tc)->haveSecurity() : false;
189}
190
191
192ArmSystem::~ArmSystem()
193{
194 if (debugPrintkEvent)
195 delete debugPrintkEvent;
196}
197
198ObjectFile *
199ArmSystem::getBootLoader(ObjectFile *const obj)
200{
201 for (auto &bl : bootLoaders) {
202 if (bl->getArch() == obj->getArch())
203 return bl.get();
204 }
205
206 return nullptr;
207}
208
209bool
210ArmSystem::haveLPAE(ThreadContext *tc)
211{
212 return FullSystem? getArmSystem(tc)->haveLPAE() : false;
213}
214
215bool
216ArmSystem::haveVirtualization(ThreadContext *tc)
217{
218 return FullSystem? getArmSystem(tc)->haveVirtualization() : false;
219}
220
221bool
222ArmSystem::highestELIs64(ThreadContext *tc)
223{
224 return FullSystem? getArmSystem(tc)->highestELIs64() : true;
225}
226
227ExceptionLevel
228ArmSystem::highestEL(ThreadContext *tc)
229{
230 return FullSystem? getArmSystem(tc)->highestEL() : EL1;
231}
232
233bool
234ArmSystem::haveEL(ThreadContext *tc, ExceptionLevel el)
235{
236 switch (el) {
237 case EL0:
238 case EL1:
239 return true;
240 case EL2:
241 return haveVirtualization(tc);
242 case EL3:
243 return haveSecurity(tc);
244 default:
245 warn("Unimplemented Exception Level\n");
246 return false;
247 }
248}
249
250Addr
251ArmSystem::resetAddr64(ThreadContext *tc)
252{
253 return getArmSystem(tc)->resetAddr64();
254}
255
256uint8_t
257ArmSystem::physAddrRange(ThreadContext *tc)
258{
259 return getArmSystem(tc)->physAddrRange();
260}
261
262Addr
263ArmSystem::physAddrMask(ThreadContext *tc)
264{
265 return getArmSystem(tc)->physAddrMask();
266}
267
268bool
269ArmSystem::haveLargeAsid64(ThreadContext *tc)
270{
271 return getArmSystem(tc)->haveLargeAsid64();
272}
273
274bool
275ArmSystem::haveSemihosting(ThreadContext *tc)
276{
277 return FullSystem && getArmSystem(tc)->haveSemihosting();
278}
279
280uint64_t
281ArmSystem::callSemihosting64(ThreadContext *tc,
282 uint32_t op, uint64_t param)
283{
284 ArmSystem *sys = getArmSystem(tc);
285 return sys->semihosting->call64(tc, op, param);
286}
287
288uint32_t
289ArmSystem::callSemihosting32(ThreadContext *tc,
290 uint32_t op, uint32_t param)
291{
292 ArmSystem *sys = getArmSystem(tc);
293 return sys->semihosting->call32(tc, op, param);
294}
295
296ArmSystem *
297ArmSystemParams::create()
298{
299 return new ArmSystem(this);
300}
301
302void
303GenericArmSystem::initState()
304{
305 // Moved from the constructor to here since it relies on the
306 // address map being resolved in the interconnect
307
308 // Call the initialisation of the super class
309 ArmSystem::initState();
310}
311
312GenericArmSystem *
313GenericArmSystemParams::create()
314{
315
316 return new GenericArmSystem(this);
317}
|