1/*
2* Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARM_PROCESS_HH__
44#define __ARM_PROCESS_HH__
45
46#include <string>
47#include <vector>
48
49#include "arch/arm/intregs.hh"
50#include "base/loader/object_file.hh"
| 1/*
2* Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARM_PROCESS_HH__
44#define __ARM_PROCESS_HH__
45
46#include <string>
47#include <vector>
48
49#include "arch/arm/intregs.hh"
50#include "base/loader/object_file.hh"
|
51#include "sim/process.hh"
52
53class LiveProcess;
54class ObjectFile;
55class System;
56
57class ArmLiveProcess : public LiveProcess
58{
59 protected:
60 ObjectFile::Arch arch;
61 ArmLiveProcess(LiveProcessParams * params, ObjectFile *objFile,
62 ObjectFile::Arch _arch);
63 template<class IntType>
64 void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
65};
66
67class ArmLiveProcess32 : public ArmLiveProcess
68{
69 protected:
70 ArmLiveProcess32(LiveProcessParams * params, ObjectFile *objFile,
71 ObjectFile::Arch _arch);
72
73 void initState();
74
75 public:
76
77 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
78 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
79 void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
80 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
81};
82
83class ArmLiveProcess64 : public ArmLiveProcess
84{
85 protected:
86 ArmLiveProcess64(LiveProcessParams * params, ObjectFile *objFile,
87 ObjectFile::Arch _arch);
88
89 void initState();
90
91 public:
92
93 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
94 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
95 void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
96 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
97};
98
99/* No architectural page table defined for this ISA */
100typedef NoArchPageTable ArchPageTable;
101
102#endif // __ARM_PROCESS_HH__
103
| 52#include "sim/process.hh"
53
54class LiveProcess;
55class ObjectFile;
56class System;
57
58class ArmLiveProcess : public LiveProcess
59{
60 protected:
61 ObjectFile::Arch arch;
62 ArmLiveProcess(LiveProcessParams * params, ObjectFile *objFile,
63 ObjectFile::Arch _arch);
64 template<class IntType>
65 void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
66};
67
68class ArmLiveProcess32 : public ArmLiveProcess
69{
70 protected:
71 ArmLiveProcess32(LiveProcessParams * params, ObjectFile *objFile,
72 ObjectFile::Arch _arch);
73
74 void initState();
75
76 public:
77
78 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
79 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
80 void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
81 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
82};
83
84class ArmLiveProcess64 : public ArmLiveProcess
85{
86 protected:
87 ArmLiveProcess64(LiveProcessParams * params, ObjectFile *objFile,
88 ObjectFile::Arch _arch);
89
90 void initState();
91
92 public:
93
94 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
95 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
96 void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
97 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
98};
99
100/* No architectural page table defined for this ISA */
101typedef NoArchPageTable ArchPageTable;
102
103#endif // __ARM_PROCESS_HH__
104
|