str.isa (8136:afcb66f4b964) str.isa (8301:858384f3af1c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 138 unchanged lines hidden (view full) ---

147 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
148 else:
149 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
150
151 class StoreRegInst(StoreInst):
152 def __init__(self, *args, **kargs):
153 super(StoreRegInst, self).__init__(*args, **kargs)
154 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 138 unchanged lines hidden (view full) ---

147 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
148 else:
149 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
150
151 class StoreRegInst(StoreInst):
152 def __init__(self, *args, **kargs):
153 super(StoreRegInst, self).__init__(*args, **kargs)
154 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
155 " shiftType, CondCodes<29:>)"
155 " shiftType, CondCodesF<29:>)"
156 if self.add:
157 self.wbDecl = '''
158 MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
159 '''
160 else:
161 self.wbDecl = '''
162 MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
163 '''

--- 221 unchanged lines hidden --- 		156 if self.add:
157 self.wbDecl = '''
158 MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
159 '''
160 else:
161 self.wbDecl = '''
162 MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
163 '''

--- 221 unchanged lines hidden ---