str.isa (7644:62873d5c2bfc) str.isa (7646:a444dbee8c07)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 53 unchanged lines hidden (view full) ---

62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = { "postacc_code" : "" }
69
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 53 unchanged lines hidden (view full) ---

62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = { "postacc_code" : "" }
69
70 def emitHelper(self, base = 'Memory'):
70 def emitHelper(self, base = 'Memory', wbDecl = None):
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
79 self.memFlags, [], base)
79 self.memFlags, [], base, wbDecl)
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class SrsInst(LoadStoreInst):
86 execBase = 'Store'
87 decConstBase = 'Srs'

--- 44 unchanged lines hidden (view full) ---

132 decoder_output += newDecoder
133 exec_output += newExec
134
135 class StoreImmInst(StoreInst):
136 def __init__(self, *args, **kargs):
137 super(StoreImmInst, self).__init__(*args, **kargs)
138 self.offset = self.op + " imm"
139
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class SrsInst(LoadStoreInst):
86 execBase = 'Store'
87 decConstBase = 'Srs'

--- 44 unchanged lines hidden (view full) ---

132 decoder_output += newDecoder
133 exec_output += newExec
134
135 class StoreImmInst(StoreInst):
136 def __init__(self, *args, **kargs):
137 super(StoreImmInst, self).__init__(*args, **kargs)
138 self.offset = self.op + " imm"
139
140 if self.add:
141 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
142 else:
143 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
144
140 class StoreRegInst(StoreInst):
141 def __init__(self, *args, **kargs):
142 super(StoreRegInst, self).__init__(*args, **kargs)
143 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
144 " shiftType, CondCodes<29:>)"
145 class StoreRegInst(StoreInst):
146 def __init__(self, *args, **kargs):
147 super(StoreRegInst, self).__init__(*args, **kargs)
148 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
149 " shiftType, CondCodes<29:>)"
150 if self.add:
151 self.wbDecl = '''
152 MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
153 '''
154 else:
155 self.wbDecl = '''
156 MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
157 '''
145
146 class StoreSingle(StoreInst):
147 def __init__(self, *args, **kargs):
148 super(StoreSingle, self).__init__(*args, **kargs)
149
150 # Build the default class name
151 self.Name = self.nameFunc(self.post, self.add, self.writeback,
152 self.size, self.sign, self.user)

--- 28 unchanged lines hidden (view full) ---

181 if self.flavor == "fp":
182 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
183 else:
184 accCode = \
185 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
186 accCode = accCode % \
187 { "suffix" : buildMemSuffix(self.sign, self.size) }
188
158
159 class StoreSingle(StoreInst):
160 def __init__(self, *args, **kargs):
161 super(StoreSingle, self).__init__(*args, **kargs)
162
163 # Build the default class name
164 self.Name = self.nameFunc(self.post, self.add, self.writeback,
165 self.size, self.sign, self.user)

--- 28 unchanged lines hidden (view full) ---

194 if self.flavor == "fp":
195 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
196 else:
197 accCode = \
198 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
199 accCode = accCode % \
200 { "suffix" : buildMemSuffix(self.sign, self.size) }
201
189 if self.writeback:
190 accCode += "Base = Base %s;\n" % self.offset
191
192 self.codeBlobs["memacc_code"] = accCode
193
194 # Push it out to the output files
195 base = buildMemBase(self.basePrefix, self.post, self.writeback)
202 self.codeBlobs["memacc_code"] = accCode
203
204 # Push it out to the output files
205 base = buildMemBase(self.basePrefix, self.post, self.writeback)
196 self.emitHelper(base)
206 wbDecl = None
207 if self.writeback:
208 wbDecl = self.wbDecl
209 self.emitHelper(base, wbDecl)
197
198 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
199 return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
200
201 class StoreImmEx(StoreImmInst, StoreSingle):
202 execBase = 'StoreEx'
203 decConstBase = 'StoreExImm'
204 basePrefix = 'MemoryExImm'

--- 7 unchanged lines hidden (view full) ---

212 decConstBase = 'LoadStoreImm'
213 basePrefix = 'MemoryImm'
214 nameFunc = staticmethod(storeImmClassName)
215
216 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
217 return memClassName("STORE_REG", post, add, writeback, size, sign, user)
218
219 class StoreReg(StoreRegInst, StoreSingle):
210
211 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
212 return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
213
214 class StoreImmEx(StoreImmInst, StoreSingle):
215 execBase = 'StoreEx'
216 decConstBase = 'StoreExImm'
217 basePrefix = 'MemoryExImm'

--- 7 unchanged lines hidden (view full) ---

225 decConstBase = 'LoadStoreImm'
226 basePrefix = 'MemoryImm'
227 nameFunc = staticmethod(storeImmClassName)
228
229 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
230 return memClassName("STORE_REG", post, add, writeback, size, sign, user)
231
232 class StoreReg(StoreRegInst, StoreSingle):
220 decConstBase = 'LoadStoreReg'
233 decConstBase = 'StoreReg'
221 basePrefix = 'MemoryReg'
222 nameFunc = staticmethod(storeRegClassName)
223
224 class StoreDouble(StoreInst):
225 def __init__(self, *args, **kargs):
226 super(StoreDouble, self).__init__(*args, **kargs)
227
228 # Build the default class name

--- 31 unchanged lines hidden (view full) ---

260 '''
261 else:
262 accCode = '''
263 CPSR cpsr = Cpsr;
264 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
265 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
266 '''
267
234 basePrefix = 'MemoryReg'
235 nameFunc = staticmethod(storeRegClassName)
236
237 class StoreDouble(StoreInst):
238 def __init__(self, *args, **kargs):
239 super(StoreDouble, self).__init__(*args, **kargs)
240
241 # Build the default class name

--- 31 unchanged lines hidden (view full) ---

273 '''
274 else:
275 accCode = '''
276 CPSR cpsr = Cpsr;
277 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
278 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
279 '''
280
268 if self.writeback:
269 accCode += "Base = Base %s;\n" % self.offset
270
271 self.codeBlobs["memacc_code"] = accCode
272
273 # Push it out to the output files
274 base = buildMemBase(self.basePrefix, self.post, self.writeback)
281 self.codeBlobs["memacc_code"] = accCode
282
283 # Push it out to the output files
284 base = buildMemBase(self.basePrefix, self.post, self.writeback)
275 self.emitHelper(base)
285 wbDecl = None
286 if self.writeback:
287 wbDecl = self.wbDecl
288 self.emitHelper(base, wbDecl)
276
277 def storeDoubleImmClassName(post, add, writeback):
278 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
279
280 class StoreDoubleImmEx(StoreImmInst, StoreDouble):
281 execBase = 'StoreEx'
282 decConstBase = 'StoreExDImm'
283 basePrefix = 'MemoryExDImm'

--- 7 unchanged lines hidden (view full) ---

291 decConstBase = 'LoadStoreDImm'
292 basePrefix = 'MemoryDImm'
293 nameFunc = staticmethod(storeDoubleImmClassName)
294
295 def storeDoubleRegClassName(post, add, writeback):
296 return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
297
298 class StoreDoubleReg(StoreRegInst, StoreDouble):
289
290 def storeDoubleImmClassName(post, add, writeback):
291 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
292
293 class StoreDoubleImmEx(StoreImmInst, StoreDouble):
294 execBase = 'StoreEx'
295 decConstBase = 'StoreExDImm'
296 basePrefix = 'MemoryExDImm'

--- 7 unchanged lines hidden (view full) ---

304 decConstBase = 'LoadStoreDImm'
305 basePrefix = 'MemoryDImm'
306 nameFunc = staticmethod(storeDoubleImmClassName)
307
308 def storeDoubleRegClassName(post, add, writeback):
309 return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
310
311 class StoreDoubleReg(StoreRegInst, StoreDouble):
299 decConstBase = 'LoadStoreDReg'
312 decConstBase = 'StoreDReg'
300 basePrefix = 'MemoryDReg'
301 nameFunc = staticmethod(storeDoubleRegClassName)
302
303 def buildStores(mnem, size=4, sign=False, user=False):
304 StoreImm(mnem, True, True, True, size, sign, user).emit()
305 StoreReg(mnem, True, True, True, size, sign, user).emit()
306 StoreImm(mnem, True, False, True, size, sign, user).emit()
307 StoreReg(mnem, True, False, True, size, sign, user).emit()

--- 54 unchanged lines hidden --- 		313 basePrefix = 'MemoryDReg'
314 nameFunc = staticmethod(storeDoubleRegClassName)
315
316 def buildStores(mnem, size=4, sign=False, user=False):
317 StoreImm(mnem, True, True, True, size, sign, user).emit()
318 StoreReg(mnem, True, True, True, size, sign, user).emit()
319 StoreImm(mnem, True, False, True, size, sign, user).emit()
320 StoreReg(mnem, True, False, True, size, sign, user).emit()

--- 54 unchanged lines hidden ---