| str.isa (7404:bfc74724914e) | str.isa (7590:27dbb92bbad5) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 29 unchanged lines hidden (view full) --- 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 29 unchanged lines hidden (view full) --- 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 |
| 46 def storeImmClassName(post, add, writeback, \ 47 size=4, sign=False, user=False): 48 return memClassName("STORE_IMM", post, add, writeback, 49 size, sign, user) | 46 class StoreInst(LoadStoreInst): 47 execBase = 'Store' |
| 50 | 48 |
| 51 def storeRegClassName(post, add, writeback, \ 52 size=4, sign=False, user=False): 53 return memClassName("STORE_REG", post, add, writeback, 54 size, sign, user) | 49 def __init__(self, mnem, post, add, writeback, size=4, 50 sign=False, user=False, flavor="normal"): 51 super(StoreInst, self).__init__() |
| 55 | 52 |
| 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) | 53 self.name = mnem 54 self.post = post 55 self.add = add 56 self.writeback = writeback 57 self.size = size 58 self.sign = sign 59 self.user = user 60 self.flavor = flavor |
| 59 | 61 |
| 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) | 62 if self.add: 63 self.op = " +" 64 else: 65 self.op = " -" |
| 63 | 66 |
| 64 def emitStore(name, Name, imm, eaCode, accCode, postAccCode, \ 65 memFlags, instFlags, base, double=False, strex=False, 66 execTemplateBase = 'Store'): 67 global header_output, decoder_output, exec_output | 67 self.memFlags = ["ArmISA::TLB::MustBeOne"] 68 self.codeBlobs = { "postacc_code" : "" } |
| 68 | 69 |
| 69 (newHeader, 70 newDecoder, 71 newExec) = loadStoreBase(name, Name, imm, 72 eaCode, accCode, postAccCode, 73 memFlags, instFlags, double, strex, 74 base, execTemplateBase = execTemplateBase) | 70 def emitHelper(self, base = 'Memory'): |
| 75 | 71 |
| 76 header_output += newHeader 77 decoder_output += newDecoder 78 exec_output += newExec | 72 global header_output, decoder_output, exec_output |
| 79 | 73 |
| 80 def buildImmStore(mnem, post, add, writeback, \ 81 size=4, sign=False, user=False, \ 82 strex=False, vstr=False): 83 name = mnem 84 Name = storeImmClassName(post, add, writeback, \ 85 size, sign, user) | 74 codeBlobs = self.codeBlobs 75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 76 (newHeader, 77 newDecoder, 78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 79 self.memFlags, [], base) |
| 86 | 80 |
| 87 if add: 88 op = " +" 89 else: 90 op = " -" | 81 header_output += newHeader 82 decoder_output += newDecoder 83 exec_output += newExec |
| 91 | 84 |
| 92 offset = op + " imm" 93 eaCode = "EA = Base" 94 if not post: 95 eaCode += offset 96 eaCode += ";" | 85 class SrsInst(LoadStoreInst): 86 execBase = 'Store' 87 decConstBase = 'Srs' |
| 97 | 88 |
| 98 if vstr: | 89 def __init__(self, mnem, post, add, writeback): 90 super(SrsInst, self).__init__() 91 self.name = mnem 92 self.post = post 93 self.add = add 94 self.writeback = writeback 95 96 self.Name = "SRS_" + storeImmClassName(post, add, writeback, 8) 97 98 def emit(self): 99 offset = 0 100 if self.post != self.add: 101 offset += 4 102 if not self.add: 103 offset -= 8 104 105 eaCode = "EA = SpMode + %d;" % offset 106 107 wbDiff = -8 108 if self.add: 109 wbDiff = 8 |
| 99 accCode = ''' | 110 accCode = ''' |
| 100 Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e); 101 ''' % { "suffix" : buildMemSuffix(sign, size) } 102 else: 103 accCode = ''' 104 Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e); 105 ''' % { "suffix" : buildMemSuffix(sign, size) } 106 if writeback: 107 accCode += "Base = Base %s;\n" % offset | 111 CPSR cpsr = Cpsr; 112 Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) | 113 ((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32); 114 ''' 115 if self.writeback: 116 accCode += "SpMode = SpMode + %s;\n" % wbDiff |
| 108 | 117 |
| 109 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] 110 if user: 111 memFlags.append("ArmISA::TLB::UserMode") | 118 global header_output, decoder_output, exec_output |
| 112 | 119 |
| 113 if strex: 114 memFlags.append("Request::LLSC") 115 Name = "%s_%s" % (mnem.upper(), Name) 116 base = buildMemBase("MemoryExImm", post, writeback) 117 postAccCode = "Result = !writeResult;" 118 execTemplateBase = 'StoreEx' 119 else: 120 if vstr: 121 Name = "%s_%s" % (mnem.upper(), Name) 122 else: 123 memFlags.append("ArmISA::TLB::AllowUnaligned") 124 base = buildMemBase("MemoryImm", post, writeback) 125 postAccCode = "" 126 execTemplateBase = 'Store' | 120 codeBlobs = { "ea_code": eaCode, 121 "memacc_code": accCode, 122 "postacc_code": "" } 123 codeBlobs["predicate_test"] = pickPredicate(codeBlobs) |
| 127 | 124 |
| 128 emitStore(name, Name, True, eaCode, accCode, postAccCode, \ 129 memFlags, [], base, strex=strex, 130 execTemplateBase = execTemplateBase) | 125 (newHeader, 126 newDecoder, 127 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 128 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [], 129 base = 'SrsOp') |
| 131 | 130 |
| 132 def buildSrsStore(mnem, post, add, writeback): 133 name = mnem 134 Name = "SRS_" + storeImmClassName(post, add, writeback, 8) | 131 header_output += newHeader 132 decoder_output += newDecoder 133 exec_output += newExec |
| 135 | 134 |
| 136 offset = 0 137 if post != add: 138 offset += 4 139 if not add: 140 offset -= 8 | 135 class StoreImmInst(StoreInst): 136 def __init__(self, *args, **kargs): 137 super(StoreImmInst, self).__init__(*args, **kargs) 138 self.offset = self.op + " imm" |
| 141 | 139 |
| 142 eaCode = "EA = SpMode + %d;" % offset | 140 class StoreRegInst(StoreInst): 141 def __init__(self, *args, **kargs): 142 super(StoreRegInst, self).__init__(*args, **kargs) 143 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 144 " shiftType, CondCodes<29:>)" |
| 143 | 145 |
| 144 wbDiff = -8 145 if add: 146 wbDiff = 8 147 accCode = ''' 148 CPSR cpsr = Cpsr; 149 Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) | 150 ((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32); 151 ''' 152 if writeback: 153 accCode += "SpMode = SpMode + %s;\n" % wbDiff | 146 class StoreSingle(StoreInst): 147 def __init__(self, *args, **kargs): 148 super(StoreSingle, self).__init__(*args, **kargs) |
| 154 | 149 |
| 155 global header_output, decoder_output, exec_output | 150 # Build the default class name 151 self.Name = self.nameFunc(self.post, self.add, self.writeback, 152 self.size, self.sign, self.user) |
| 156 | 153 |
| 157 (newHeader, 158 newDecoder, 159 newExec) = SrsBase(name, Name, eaCode, accCode, 160 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], []) | 154 # Add memory request flags where necessary 155 self.memFlags.append("%d" % (self.size - 1)) 156 if self.user: 157 self.memFlags.append("ArmISA::TLB::UserMode") |
| 161 | 158 |
| 162 header_output += newHeader 163 decoder_output += newDecoder 164 exec_output += newExec | 159 if self.flavor == "exclusive": 160 self.memFlags.append("Request::LLSC") 161 elif self.flavor != "fp": 162 self.memFlags.append("ArmISA::TLB::AllowUnaligned") |
| 165 | 163 |
| 166 def buildRegStore(mnem, post, add, writeback, \ 167 size=4, sign=False, user=False, strex=False): 168 name = mnem 169 Name = storeRegClassName(post, add, writeback, 170 size, sign, user) | 164 # Disambiguate the class name for different flavors of stores 165 if self.flavor != "normal": 166 self.Name = "%s_%s" % (self.name.upper(), self.Name) |
| 171 | 167 |
| 172 if add: 173 op = " +" 174 else: 175 op = " -" | 168 def emit(self): 169 # Address computation 170 eaCode = "EA = Base" 171 if not self.post: 172 eaCode += self.offset 173 eaCode += ";" 174 self.codeBlobs["ea_code"] = eaCode |
| 176 | 175 |
| 177 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 178 " shiftType, CondCodes<29:>)" 179 eaCode = "EA = Base" 180 if not post: 181 eaCode += offset 182 eaCode += ";" | 176 # Code that actually handles the access 177 if self.flavor == "fp": 178 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);' 179 else: 180 accCode = \ 181 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);' 182 accCode = accCode % \ 183 { "suffix" : buildMemSuffix(self.sign, self.size) } |
| 183 | 184 |
| 184 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 185 { "suffix" : buildMemSuffix(sign, size) } 186 if writeback: 187 accCode += "Base = Base %s;\n" % offset 188 base = buildMemBase("MemoryReg", post, writeback) | 185 if self.writeback: 186 accCode += "Base = Base %s;\n" % self.offset |
| 189 | 187 |
| 190 memFlags = ["ArmISA::TLB::MustBeOne", \ 191 "ArmISA::TLB::AllowUnaligned", \ 192 "%d" % (size - 1)] 193 if user: 194 memFlags.append("ArmISA::TLB::UserMode") | 188 self.codeBlobs["memacc_code"] = accCode |
| 195 | 189 |
| 196 emitStore(name, Name, False, eaCode, accCode, "",\ 197 memFlags, [], base) | 190 # Push it out to the output files 191 base = buildMemBase(self.basePrefix, self.post, self.writeback) 192 self.emitHelper(base) |
| 198 | 193 |
| 199 def buildDoubleImmStore(mnem, post, add, writeback, \ 200 strex=False, vstr=False): 201 name = mnem 202 Name = storeDoubleImmClassName(post, add, writeback) | 194 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False): 195 return memClassName("STORE_IMM", post, add, writeback, size, sign, user) |
| 203 | 196 |
| 204 if add: 205 op = " +" 206 else: 207 op = " -" | 197 class StoreImmEx(StoreImmInst, StoreSingle): 198 execBase = 'StoreEx' 199 decConstBase = 'StoreExImm' 200 basePrefix = 'MemoryExImm' 201 nameFunc = staticmethod(storeImmClassName) |
| 208 | 202 |
| 209 offset = op + " imm" 210 eaCode = "EA = Base" 211 if not post: 212 eaCode += offset 213 eaCode += ";" | 203 def __init__(self, *args, **kargs): 204 super(StoreImmEx, self).__init__(*args, **kargs) 205 self.codeBlobs["postacc_code"] = "Result = !writeResult;" |
| 214 | 206 |
| 215 if vstr: 216 accCode = ''' 217 uint64_t swappedMem = (uint64_t)FpDest.uw | 218 ((uint64_t)FpDest2.uw << 32); 219 Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e); 220 ''' 221 else: 222 accCode = ''' 223 CPSR cpsr = Cpsr; 224 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 225 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 226 ''' 227 if writeback: 228 accCode += "Base = Base %s;\n" % offset | 207 class StoreImm(StoreImmInst, StoreSingle): 208 decConstBase = 'LoadStoreImm' 209 basePrefix = 'MemoryImm' 210 nameFunc = staticmethod(storeImmClassName) |
| 229 | 211 |
| 230 memFlags = ["ArmISA::TLB::MustBeOne", 231 "ArmISA::TLB::AlignWord"] 232 if strex: 233 memFlags.append("Request::LLSC") 234 base = buildMemBase("MemoryExDImm", post, writeback) 235 postAccCode = "Result = !writeResult;" 236 else: 237 base = buildMemBase("MemoryDImm", post, writeback) 238 postAccCode = "" 239 if vstr or strex: 240 Name = "%s_%s" % (mnem.upper(), Name) | 212 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False): 213 return memClassName("STORE_REG", post, add, writeback, size, sign, user) |
| 241 | 214 |
| 242 emitStore(name, Name, True, eaCode, accCode, postAccCode, \ 243 memFlags, [], base, double=True, strex=strex) | 215 class StoreReg(StoreRegInst, StoreSingle): 216 decConstBase = 'LoadStoreReg' 217 basePrefix = 'MemoryReg' 218 nameFunc = staticmethod(storeRegClassName) |
| 244 | 219 |
| 245 def buildDoubleRegStore(mnem, post, add, writeback): 246 name = mnem 247 Name = storeDoubleRegClassName(post, add, writeback) | 220 class StoreDouble(StoreInst): 221 def __init__(self, *args, **kargs): 222 super(StoreDouble, self).__init__(*args, **kargs) |
| 248 | 223 |
| 249 if add: 250 op = " +" 251 else: 252 op = " -" | 224 # Build the default class name 225 self.Name = self.nameFunc(self.post, self.add, self.writeback) |
| 253 | 226 |
| 254 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 255 " shiftType, CondCodes<29:>)" 256 eaCode = "EA = Base" 257 if not post: 258 eaCode += offset 259 eaCode += ";" | 227 # Add memory request flags where necessary 228 self.memFlags.append("ArmISA::TLB::AlignWord") 229 if self.flavor == "exclusive": 230 self.memFlags.append("Request::LLSC") |
| 260 | 231 |
| 261 accCode = ''' 262 CPSR cpsr = Cpsr; 263 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 264 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 265 ''' 266 if writeback: 267 accCode += "Base = Base %s;\n" % offset 268 base = buildMemBase("MemoryDReg", post, writeback) | 232 # Disambiguate the class name for different flavors of stores 233 if self.flavor != "normal": 234 self.Name = "%s_%s" % (self.name.upper(), self.Name) |
| 269 | 235 |
| 270 memFlags = ["ArmISA::TLB::MustBeOne", 271 "ArmISA::TLB::AlignWord"] | 236 def emit(self): 237 # Address computation code 238 eaCode = "EA = Base" 239 if not self.post: 240 eaCode += self.offset 241 eaCode += ";" 242 self.codeBlobs["ea_code"] = eaCode |
| 272 | 243 |
| 273 emitStore(name, Name, False, eaCode, accCode, "", \ 274 memFlags, [], base, double=True) | 244 # Code that actually handles the access 245 if self.flavor == "fp": 246 accCode = ''' 247 uint64_t swappedMem = (uint64_t)FpDest.uw | 248 ((uint64_t)FpDest2.uw << 32); 249 Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e); 250 ''' 251 else: 252 accCode = ''' 253 CPSR cpsr = Cpsr; 254 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 255 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 256 ''' |
| 275 | 257 |
| 258 if self.writeback: 259 accCode += "Base = Base %s;\n" % self.offset 260 261 self.codeBlobs["memacc_code"] = accCode 262 263 # Push it out to the output files 264 base = buildMemBase(self.basePrefix, self.post, self.writeback) 265 self.emitHelper(base) 266 267 def storeDoubleImmClassName(post, add, writeback): 268 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False) 269 270 class StoreDoubleImmEx(StoreImmInst, StoreDouble): 271 execBase = 'StoreEx' 272 decConstBase = 'StoreExDImm' 273 basePrefix = 'MemoryExDImm' 274 nameFunc = staticmethod(storeDoubleImmClassName) 275 276 def __init__(self, *args, **kargs): 277 super(StoreDoubleImmEx, self).__init__(*args, **kargs) 278 self.codeBlobs["postacc_code"] = "Result = !writeResult;" 279 280 class StoreDoubleImm(StoreImmInst, StoreDouble): 281 decConstBase = 'LoadStoreDImm' 282 basePrefix = 'MemoryDImm' 283 nameFunc = staticmethod(storeDoubleImmClassName) 284 285 def storeDoubleRegClassName(post, add, writeback): 286 return memClassName("STORE_REGD", post, add, writeback, 4, False, False) 287 288 class StoreDoubleReg(StoreRegInst, StoreDouble): 289 decConstBase = 'LoadStoreDReg' 290 basePrefix = 'MemoryDReg' 291 nameFunc = staticmethod(storeDoubleRegClassName) 292 |
|
| 276 def buildStores(mnem, size=4, sign=False, user=False): | 293 def buildStores(mnem, size=4, sign=False, user=False): |
| 277 buildImmStore(mnem, True, True, True, size, sign, user) 278 buildRegStore(mnem, True, True, True, size, sign, user) 279 buildImmStore(mnem, True, False, True, size, sign, user) 280 buildRegStore(mnem, True, False, True, size, sign, user) 281 buildImmStore(mnem, False, True, True, size, sign, user) 282 buildRegStore(mnem, False, True, True, size, sign, user) 283 buildImmStore(mnem, False, False, True, size, sign, user) 284 buildRegStore(mnem, False, False, True, size, sign, user) 285 buildImmStore(mnem, False, True, False, size, sign, user) 286 buildRegStore(mnem, False, True, False, size, sign, user) 287 buildImmStore(mnem, False, False, False, size, sign, user) 288 buildRegStore(mnem, False, False, False, size, sign, user) | 294 StoreImm(mnem, True, True, True, size, sign, user).emit() 295 StoreReg(mnem, True, True, True, size, sign, user).emit() 296 StoreImm(mnem, True, False, True, size, sign, user).emit() 297 StoreReg(mnem, True, False, True, size, sign, user).emit() 298 StoreImm(mnem, False, True, True, size, sign, user).emit() 299 StoreReg(mnem, False, True, True, size, sign, user).emit() 300 StoreImm(mnem, False, False, True, size, sign, user).emit() 301 StoreReg(mnem, False, False, True, size, sign, user).emit() 302 StoreImm(mnem, False, True, False, size, sign, user).emit() 303 StoreReg(mnem, False, True, False, size, sign, user).emit() 304 StoreImm(mnem, False, False, False, size, sign, user).emit() 305 StoreReg(mnem, False, False, False, size, sign, user).emit() |
| 289 290 def buildDoubleStores(mnem): | 306 307 def buildDoubleStores(mnem): |
| 291 buildDoubleImmStore(mnem, True, True, True) 292 buildDoubleRegStore(mnem, True, True, True) 293 buildDoubleImmStore(mnem, True, False, True) 294 buildDoubleRegStore(mnem, True, False, True) 295 buildDoubleImmStore(mnem, False, True, True) 296 buildDoubleRegStore(mnem, False, True, True) 297 buildDoubleImmStore(mnem, False, False, True) 298 buildDoubleRegStore(mnem, False, False, True) 299 buildDoubleImmStore(mnem, False, True, False) 300 buildDoubleRegStore(mnem, False, True, False) 301 buildDoubleImmStore(mnem, False, False, False) 302 buildDoubleRegStore(mnem, False, False, False) | 308 StoreDoubleImm(mnem, True, True, True).emit() 309 StoreDoubleReg(mnem, True, True, True).emit() 310 StoreDoubleImm(mnem, True, False, True).emit() 311 StoreDoubleReg(mnem, True, False, True).emit() 312 StoreDoubleImm(mnem, False, True, True).emit() 313 StoreDoubleReg(mnem, False, True, True).emit() 314 StoreDoubleImm(mnem, False, False, True).emit() 315 StoreDoubleReg(mnem, False, False, True).emit() 316 StoreDoubleImm(mnem, False, True, False).emit() 317 StoreDoubleReg(mnem, False, True, False).emit() 318 StoreDoubleImm(mnem, False, False, False).emit() 319 StoreDoubleReg(mnem, False, False, False).emit() |
| 303 304 def buildSrsStores(mnem): | 320 321 def buildSrsStores(mnem): |
| 305 buildSrsStore(mnem, True, True, True) 306 buildSrsStore(mnem, True, True, False) 307 buildSrsStore(mnem, True, False, True) 308 buildSrsStore(mnem, True, False, False) 309 buildSrsStore(mnem, False, True, True) 310 buildSrsStore(mnem, False, True, False) 311 buildSrsStore(mnem, False, False, True) 312 buildSrsStore(mnem, False, False, False) | 322 SrsInst(mnem, True, True, True).emit() 323 SrsInst(mnem, True, True, False).emit() 324 SrsInst(mnem, True, False, True).emit() 325 SrsInst(mnem, True, False, False).emit() 326 SrsInst(mnem, False, True, True).emit() 327 SrsInst(mnem, False, True, False).emit() 328 SrsInst(mnem, False, False, True).emit() 329 SrsInst(mnem, False, False, False).emit() |
| 313 314 buildStores("str") 315 buildStores("strt", user=True) 316 buildStores("strb", size=1) 317 buildStores("strbt", size=1, user=True) 318 buildStores("strh", size=2) 319 buildStores("strht", size=2, user=True) 320 321 buildSrsStores("srs") 322 323 buildDoubleStores("strd") 324 | 330 331 buildStores("str") 332 buildStores("strt", user=True) 333 buildStores("strb", size=1) 334 buildStores("strbt", size=1, user=True) 335 buildStores("strh", size=2) 336 buildStores("strht", size=2, user=True) 337 338 buildSrsStores("srs") 339 340 buildDoubleStores("strd") 341 |
| 325 buildImmStore("strex", False, True, False, size=4, strex=True) 326 buildImmStore("strexh", False, True, False, size=2, strex=True) 327 buildImmStore("strexb", False, True, False, size=1, strex=True) 328 buildDoubleImmStore("strexd", False, True, False, strex=True) | 342 StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit() 343 StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit() 344 StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit() 345 StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit() |
| 329 | 346 |
| 330 buildImmStore("vstr", False, True, False, size=4, vstr=True) 331 buildImmStore("vstr", False, False, False, size=4, vstr=True) 332 buildDoubleImmStore("vstr", False, True, False, vstr=True) 333 buildDoubleImmStore("vstr", False, False, False, vstr=True) | 347 StoreImm("vstr", False, True, False, size=4, flavor="fp").emit() 348 StoreImm("vstr", False, False, False, size=4, flavor="fp").emit() 349 StoreDoubleImm("vstr", False, True, False, flavor="fp").emit() 350 StoreDoubleImm("vstr", False, False, False, flavor="fp").emit() |
| 334}}; | 351}}; |