str.isa (7345:4e7dc0c3f148) str.isa (7404:bfc74724914e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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102 else:
103 accCode = '''
104 Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);
105 ''' % { "suffix" : buildMemSuffix(sign, size) }
106 if writeback:
107 accCode += "Base = Base %s;\n" % offset
108
109 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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102 else:
103 accCode = '''
104 Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);
105 ''' % { "suffix" : buildMemSuffix(sign, size) }
106 if writeback:
107 accCode += "Base = Base %s;\n" % offset
108
109 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
110 if user:
111 memFlags.append("ArmISA::TLB::UserMode")
112
110 if strex:
111 memFlags.append("Request::LLSC")
112 Name = "%s_%s" % (mnem.upper(), Name)
113 base = buildMemBase("MemoryExImm", post, writeback)
114 postAccCode = "Result = !writeResult;"
115 execTemplateBase = 'StoreEx'
116 else:
117 if vstr:

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179 eaCode += ";"
180
181 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
182 { "suffix" : buildMemSuffix(sign, size) }
183 if writeback:
184 accCode += "Base = Base %s;\n" % offset
185 base = buildMemBase("MemoryReg", post, writeback)
186
113 if strex:
114 memFlags.append("Request::LLSC")
115 Name = "%s_%s" % (mnem.upper(), Name)
116 base = buildMemBase("MemoryExImm", post, writeback)
117 postAccCode = "Result = !writeResult;"
118 execTemplateBase = 'StoreEx'
119 else:
120 if vstr:

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182 eaCode += ";"
183
184 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
185 { "suffix" : buildMemSuffix(sign, size) }
186 if writeback:
187 accCode += "Base = Base %s;\n" % offset
188 base = buildMemBase("MemoryReg", post, writeback)
189
187 emitStore(name, Name, False, eaCode, accCode, "",\
188 ["ArmISA::TLB::MustBeOne", \
190 memFlags = ["ArmISA::TLB::MustBeOne", \
189 "ArmISA::TLB::AllowUnaligned", \
191 "ArmISA::TLB::AllowUnaligned", \
190 "%d" % (size - 1)], [], base)
192 "%d" % (size - 1)]
193 if user:
194 memFlags.append("ArmISA::TLB::UserMode")
191
195
196 emitStore(name, Name, False, eaCode, accCode, "",\
197 memFlags, [], base)
198
192 def buildDoubleImmStore(mnem, post, add, writeback, \
193 strex=False, vstr=False):
194 name = mnem
195 Name = storeDoubleImmClassName(post, add, writeback)
196
197 if add:
198 op = " +"
199 else:

--- 128 unchanged lines hidden --- 		199 def buildDoubleImmStore(mnem, post, add, writeback, \
200 strex=False, vstr=False):
201 name = mnem
202 Name = storeDoubleImmClassName(post, add, writeback)
203
204 if add:
205 op = " +"
206 else:

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