str.isa (7128:01b4fff80dda) str.isa (7132:83b433d6e600)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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61 return memClassName("STORE_REGD", post, add, writeback,
62 4, False, False)
63
64 def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
65 global header_output, decoder_output, exec_output
66
67 (newHeader,
68 newDecoder,
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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61 return memClassName("STORE_REGD", post, add, writeback,
62 4, False, False)
63
64 def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
65 global header_output, decoder_output, exec_output
66
67 (newHeader,
68 newDecoder,
69 newExec) = newLoadStoreBase(name, Name, imm,
70 eaCode, accCode,
71 memFlags, instFlags,
72 base, execTemplateBase = 'Store')
69 newExec) = loadStoreBase(name, Name, imm,
70 eaCode, accCode,
71 memFlags, instFlags,
72 base, execTemplateBase = 'Store')
73
74 header_output += newHeader
75 decoder_output += newDecoder
76 exec_output += newExec
77
78 def buildImmStore(mnem, post, add, writeback, \
79 size=4, sign=False, user=False):
80 name = mnem

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90 eaCode = "EA = Base"
91 if not post:
92 eaCode += offset
93 eaCode += ";"
94
95 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
96 if writeback:
97 accCode += "Base = Base %s;\n" % offset
73
74 header_output += newHeader
75 decoder_output += newDecoder
76 exec_output += newExec
77
78 def buildImmStore(mnem, post, add, writeback, \
79 size=4, sign=False, user=False):
80 name = mnem

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90 eaCode = "EA = Base"
91 if not post:
92 eaCode += offset
93 eaCode += ";"
94
95 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
96 if writeback:
97 accCode += "Base = Base %s;\n" % offset
98 base = buildMemBase("MemoryNewImm", post, writeback)
98 base = buildMemBase("MemoryImm", post, writeback)
99
100 emitStore(name, Name, True, eaCode, accCode, [], [], base)
101
102 def buildRegStore(mnem, post, add, writeback, \
103 size=4, sign=False, user=False):
104 name = mnem
105 Name = storeRegClassName(post, add, writeback,
106 size, sign, user)

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115 eaCode = "EA = Base"
116 if not post:
117 eaCode += offset
118 eaCode += ";"
119
120 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
121 if writeback:
122 accCode += "Base = Base %s;\n" % offset
99
100 emitStore(name, Name, True, eaCode, accCode, [], [], base)
101
102 def buildRegStore(mnem, post, add, writeback, \
103 size=4, sign=False, user=False):
104 name = mnem
105 Name = storeRegClassName(post, add, writeback,
106 size, sign, user)

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115 eaCode = "EA = Base"
116 if not post:
117 eaCode += offset
118 eaCode += ";"
119
120 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
121 if writeback:
122 accCode += "Base = Base %s;\n" % offset
123 base = buildMemBase("MemoryNewReg", post, writeback)
123 base = buildMemBase("MemoryReg", post, writeback)
124
125 emitStore(name, Name, False, eaCode, accCode, [], [], base)
126
127 def buildDoubleImmStore(mnem, post, add, writeback):
128 name = mnem
129 Name = storeDoubleImmClassName(post, add, writeback)
130
131 if add:

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137 eaCode = "EA = Base"
138 if not post:
139 eaCode += offset
140 eaCode += ";"
141
142 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
143 if writeback:
144 accCode += "Base = Base %s;\n" % offset
124
125 emitStore(name, Name, False, eaCode, accCode, [], [], base)
126
127 def buildDoubleImmStore(mnem, post, add, writeback):
128 name = mnem
129 Name = storeDoubleImmClassName(post, add, writeback)
130
131 if add:

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137 eaCode = "EA = Base"
138 if not post:
139 eaCode += offset
140 eaCode += ";"
141
142 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
143 if writeback:
144 accCode += "Base = Base %s;\n" % offset
145 base = buildMemBase("MemoryNewImm", post, writeback)
145 base = buildMemBase("MemoryImm", post, writeback)
146
147 emitStore(name, Name, True, eaCode, accCode, [], [], base)
148
149 def buildDoubleRegStore(mnem, post, add, writeback):
150 name = mnem
151 Name = storeDoubleRegClassName(post, add, writeback)
152
153 if add:

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160 eaCode = "EA = Base"
161 if not post:
162 eaCode += offset
163 eaCode += ";"
164
165 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
166 if writeback:
167 accCode += "Base = Base %s;\n" % offset
146
147 emitStore(name, Name, True, eaCode, accCode, [], [], base)
148
149 def buildDoubleRegStore(mnem, post, add, writeback):
150 name = mnem
151 Name = storeDoubleRegClassName(post, add, writeback)
152
153 if add:

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160 eaCode = "EA = Base"
161 if not post:
162 eaCode += offset
163 eaCode += ";"
164
165 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
166 if writeback:
167 accCode += "Base = Base %s;\n" % offset
168 base = buildMemBase("MemoryNewReg", post, writeback)
168 base = buildMemBase("MemoryReg", post, writeback)
169
170 emitStore(name, Name, False, eaCode, accCode, [], [], base)
171
172 def buildStores(mnem, size=4, sign=False, user=False):
173 buildImmStore(mnem, True, True, True, size, sign, user)
174 buildRegStore(mnem, True, True, True, size, sign, user)
175 buildImmStore(mnem, True, False, True, size, sign, user)
176 buildRegStore(mnem, True, False, True, size, sign, user)

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170 emitStore(name, Name, False, eaCode, accCode, [], [], base)
171
172 def buildStores(mnem, size=4, sign=False, user=False):
173 buildImmStore(mnem, True, True, True, size, sign, user)
174 buildRegStore(mnem, True, True, True, size, sign, user)
175 buildImmStore(mnem, True, False, True, size, sign, user)
176 buildRegStore(mnem, True, False, True, size, sign, user)

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