str.isa (13589:13522f2a5126) str.isa (14172:bba55ff08279)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011,2017,2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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109
110 wbDiff = -8
111 if self.add:
112 wbDiff = 8
113 accCode = '''
114
115 auto tc = xc->tcBase();
116 if (badMode32(tc, static_cast<OperatingMode>(regMode))) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011,2017,2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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109
110 wbDiff = -8
111 if self.add:
112 wbDiff = 8
113 accCode = '''
114
115 auto tc = xc->tcBase();
116 if (badMode32(tc, static_cast<OperatingMode>(regMode))) {
117 return undefinedFault32(tc, opModeToEL(currOpMode(tc)));
117 return undefinedFault32(tc, currEL(tc));
118 }
119
120 CPSR cpsr = Cpsr;
121 Mem_ud = (uint64_t)cSwap(LR_uw, cpsr.e) |
122 ((uint64_t)cSwap(Spsr_uw, cpsr.e) << 32);
123 '''
124
125 global header_output, decoder_output, exec_output

--- 289 unchanged lines hidden --- 		118 }
119
120 CPSR cpsr = Cpsr;
121 Mem_ud = (uint64_t)cSwap(LR_uw, cpsr.e) |
122 ((uint64_t)cSwap(Spsr_uw, cpsr.e) << 32);
123 '''
124
125 global header_output, decoder_output, exec_output

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