1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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73 memFlags, instFlags, double, strex,
74 base, execTemplateBase = execTemplateBase)
75
76 header_output += newHeader
77 decoder_output += newDecoder
78 exec_output += newExec
79
80 def buildImmStore(mnem, post, add, writeback, \
81 size=4, sign=False, user=False, strex=False):
81 size=4, sign=False, user=False, \
82 strex=False, vstr=False):
83 name = mnem
84 Name = storeImmClassName(post, add, writeback, \
85 size, sign, user)
86
87 if add:
88 op = " +"
89 else:
90 op = " -"
91
92 offset = op + " imm"
93 eaCode = "EA = Base"
94 if not post:
95 eaCode += offset
96 eaCode += ";"
97
97 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
98 { "suffix" : buildMemSuffix(sign, size) }
98 if vstr:
99 accCode = '''
100 Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);
101 ''' % { "suffix" : buildMemSuffix(sign, size) }
102 else:
103 accCode = '''
104 Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);
105 ''' % { "suffix" : buildMemSuffix(sign, size) }
106 if writeback:
107 accCode += "Base = Base %s;\n" % offset
108
109 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
110 if strex:
111 memFlags.append("Request::LLSC")
112 Name = "%s_%s" % (mnem.upper(), Name)
113 base = buildMemBase("MemoryExImm", post, writeback)
114 postAccCode = "Result = !writeResult;"
115 execTemplateBase = 'StoreEx'
116 else:
110 memFlags.append("ArmISA::TLB::AllowUnaligned")
117 if vstr:
118 Name = "%s_%s" % (mnem.upper(), Name)
119 else:
120 memFlags.append("ArmISA::TLB::AllowUnaligned")
121 base = buildMemBase("MemoryImm", post, writeback)
122 postAccCode = ""
123 execTemplateBase = 'Store'
124
125 emitStore(name, Name, True, eaCode, accCode, postAccCode, \
126 memFlags, [], base, strex=strex,
127 execTemplateBase = execTemplateBase)
128

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184 accCode += "Base = Base %s;\n" % offset
185 base = buildMemBase("MemoryReg", post, writeback)
186
187 emitStore(name, Name, False, eaCode, accCode, "",\
188 ["ArmISA::TLB::MustBeOne", \
189 "ArmISA::TLB::AllowUnaligned", \
190 "%d" % (size - 1)], [], base)
191
182 def buildDoubleImmStore(mnem, post, add, writeback, strex=False):
192 def buildDoubleImmStore(mnem, post, add, writeback, \
193 strex=False, vstr=False):
194 name = mnem
195 Name = storeDoubleImmClassName(post, add, writeback)
196
197 if add:
198 op = " +"
199 else:
200 op = " -"
201
202 offset = op + " imm"
203 eaCode = "EA = Base"
204 if not post:
205 eaCode += offset
206 eaCode += ";"
207
197 accCode = '''
198 CPSR cpsr = Cpsr;
199 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
200 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
201 '''
208 if vstr:
209 accCode = '''
210 uint64_t swappedMem = (uint64_t)FpDest.uw |
211 ((uint64_t)FpDest2.uw << 32);
212 Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
213 '''
214 else:
215 accCode = '''
216 CPSR cpsr = Cpsr;
217 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
218 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
219 '''
220 if writeback:
221 accCode += "Base = Base %s;\n" % offset
222
223 memFlags = ["ArmISA::TLB::MustBeOne",
224 "ArmISA::TLB::AlignWord"]
225 if strex:
226 memFlags.append("Request::LLSC")
209 Name = "%s_%s" % (mnem.upper(), Name)
227 base = buildMemBase("MemoryExDImm", post, writeback)
228 postAccCode = "Result = !writeResult;"
229 else:
230 base = buildMemBase("MemoryDImm", post, writeback)
231 postAccCode = ""
232 if vstr or strex:
233 Name = "%s_%s" % (mnem.upper(), Name)
234
235 emitStore(name, Name, True, eaCode, accCode, postAccCode, \
236 memFlags, [], base, double=True, strex=strex)
237
238 def buildDoubleRegStore(mnem, post, add, writeback):
239 name = mnem
240 Name = storeDoubleRegClassName(post, add, writeback)
241

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314 buildSrsStores("srs")
315
316 buildDoubleStores("strd")
317
318 buildImmStore("strex", False, True, False, size=4, strex=True)
319 buildImmStore("strexh", False, True, False, size=2, strex=True)
320 buildImmStore("strexb", False, True, False, size=1, strex=True)
321 buildDoubleImmStore("strexd", False, True, False, strex=True)
322
323 buildImmStore("vstr", False, True, False, size=4, vstr=True)
324 buildImmStore("vstr", False, False, False, size=4, vstr=True)
325 buildDoubleImmStore("vstr", False, True, False, vstr=True)
326 buildDoubleImmStore("vstr", False, False, False, vstr=True)
327}};