1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 47 unchanged lines hidden (view full) --- 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 |
64 def emitStore(name, Name, imm, eaCode, accCode, postAccCode, \ 65 memFlags, instFlags, base, double=False, strex=False, 66 execTemplateBase = 'Store'): |
67 global header_output, decoder_output, exec_output 68 69 (newHeader, 70 newDecoder, 71 newExec) = loadStoreBase(name, Name, imm, |
72 eaCode, accCode, postAccCode, 73 memFlags, instFlags, double, strex, 74 base, execTemplateBase = execTemplateBase) |
75 76 header_output += newHeader 77 decoder_output += newDecoder 78 exec_output += newExec 79 80 def buildImmStore(mnem, post, add, writeback, \ |
81 size=4, sign=False, user=False, strex=False): |
82 name = mnem 83 Name = storeImmClassName(post, add, writeback, \ 84 size, sign, user) 85 86 if add: 87 op = " +" 88 else: 89 op = " -" 90 91 offset = op + " imm" 92 eaCode = "EA = Base" 93 if not post: 94 eaCode += offset 95 eaCode += ";" 96 97 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 98 { "suffix" : buildMemSuffix(sign, size) } 99 if writeback: 100 accCode += "Base = Base %s;\n" % offset |
101 |
102 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] 103 if strex: 104 memFlags.append("Request::LLSC") 105 Name = "%s_%s" % (mnem.upper(), Name) 106 base = buildMemBase("MemoryExImm", post, writeback) 107 postAccCode = "Result = !writeResult;" 108 execTemplateBase = 'StoreEx' 109 else: 110 memFlags.append("ArmISA::TLB::AllowUnaligned") 111 base = buildMemBase("MemoryImm", post, writeback) 112 postAccCode = "" 113 execTemplateBase = 'Store' |
114 |
115 emitStore(name, Name, True, eaCode, accCode, postAccCode, \ 116 memFlags, [], base, strex=strex, 117 execTemplateBase = execTemplateBase) 118 |
119 def buildRegStore(mnem, post, add, writeback, \ |
120 size=4, sign=False, user=False, strex=False): |
121 name = mnem 122 Name = storeRegClassName(post, add, writeback, 123 size, sign, user) 124 125 if add: 126 op = " +" 127 else: 128 op = " -" --- 6 unchanged lines hidden (view full) --- 135 eaCode += ";" 136 137 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 138 { "suffix" : buildMemSuffix(sign, size) } 139 if writeback: 140 accCode += "Base = Base %s;\n" % offset 141 base = buildMemBase("MemoryReg", post, writeback) 142 |
143 emitStore(name, Name, False, eaCode, accCode, "",\ |
144 ["ArmISA::TLB::MustBeOne", \ 145 "ArmISA::TLB::AllowUnaligned", \ 146 "%d" % (size - 1)], [], base) 147 |
148 def buildDoubleImmStore(mnem, post, add, writeback, strex=False): |
149 name = mnem 150 Name = storeDoubleImmClassName(post, add, writeback) 151 152 if add: 153 op = " +" 154 else: 155 op = " -" 156 --- 5 unchanged lines hidden (view full) --- 162 163 accCode = ''' 164 CPSR cpsr = Cpsr; 165 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 166 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 167 ''' 168 if writeback: 169 accCode += "Base = Base %s;\n" % offset |
170 |
171 memFlags = ["ArmISA::TLB::MustBeOne", 172 "ArmISA::TLB::AlignWord"] 173 if strex: 174 memFlags.append("Request::LLSC") 175 Name = "%s_%s" % (mnem.upper(), Name) 176 base = buildMemBase("MemoryExDImm", post, writeback) 177 postAccCode = "Result = !writeResult;" 178 else: 179 base = buildMemBase("MemoryDImm", post, writeback) 180 postAccCode = "" |
181 |
182 emitStore(name, Name, True, eaCode, accCode, postAccCode, \ 183 memFlags, [], base, double=True, strex=strex) 184 |
185 def buildDoubleRegStore(mnem, post, add, writeback): 186 name = mnem 187 Name = storeDoubleRegClassName(post, add, writeback) 188 189 if add: 190 op = " +" 191 else: 192 op = " -" --- 9 unchanged lines hidden (view full) --- 202 CPSR cpsr = Cpsr; 203 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 204 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 205 ''' 206 if writeback: 207 accCode += "Base = Base %s;\n" % offset 208 base = buildMemBase("MemoryDReg", post, writeback) 209 |
210 memFlags = ["ArmISA::TLB::MustBeOne", 211 "ArmISA::TLB::AlignWord"] |
212 |
213 emitStore(name, Name, False, eaCode, accCode, "", \ 214 memFlags, [], base, double=True) 215 |
216 def buildStores(mnem, size=4, sign=False, user=False): 217 buildImmStore(mnem, True, True, True, size, sign, user) 218 buildRegStore(mnem, True, True, True, size, sign, user) 219 buildImmStore(mnem, True, False, True, size, sign, user) 220 buildRegStore(mnem, True, False, True, size, sign, user) 221 buildImmStore(mnem, False, True, True, size, sign, user) 222 buildRegStore(mnem, False, True, True, size, sign, user) 223 buildImmStore(mnem, False, False, True, size, sign, user) --- 20 unchanged lines hidden (view full) --- 244 buildStores("str") 245 buildStores("strt", user=True) 246 buildStores("strb", size=1) 247 buildStores("strbt", size=1, user=True) 248 buildStores("strh", size=2) 249 buildStores("strht", size=2, user=True) 250 251 buildDoubleStores("strd") |
252 253 buildImmStore("strex", False, True, False, size=4, strex=True) 254 buildImmStore("strexh", False, True, False, size=2, strex=True) 255 buildImmStore("strexb", False, True, False, size=1, strex=True) 256 buildDoubleImmStore("strexd", False, True, False, strex=True) |
257}}; |