70c70
< def emitHelper(self, base = 'Memory'):
---
> def emitHelper(self, base = 'Memory', wbDecl = None):
79c79
< self.memFlags, [], base)
---
> self.memFlags, [], base, wbDecl)
139a140,144
> if self.add:
> self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
> else:
> self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
>
144a150,157
> if self.add:
> self.wbDecl = '''
> MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
> '''
> else:
> self.wbDecl = '''
> MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
> '''
189,191d201
< if self.writeback:
< accCode += "Base = Base %s;\n" % self.offset
<
196c206,209
< self.emitHelper(base)
---
> wbDecl = None
> if self.writeback:
> wbDecl = self.wbDecl
> self.emitHelper(base, wbDecl)
220c233
< decConstBase = 'LoadStoreReg'
---
> decConstBase = 'StoreReg'
268,270d280
< if self.writeback:
< accCode += "Base = Base %s;\n" % self.offset
<
275c285,288
< self.emitHelper(base)
---
> wbDecl = None
> if self.writeback:
> wbDecl = self.wbDecl
> self.emitHelper(base, wbDecl)
299c312
< decConstBase = 'LoadStoreDReg'
---
> decConstBase = 'StoreDReg'