55a56,63
> def storeDoubleImmClassName(post, add, writeback):
> return memClassName("STORE_IMMD", post, add, writeback,
> 4, False, False)
>
> def storeDoubleRegClassName(post, add, writeback):
> return memClassName("STORE_REGD", post, add, writeback,
> 4, False, False)
>
118a127,171
> def buildDoubleImmStore(mnem, post, add, writeback):
> name = mnem
> Name = storeDoubleImmClassName(post, add, writeback)
>
> if add:
> op = " +"
> else:
> op = " -"
>
> offset = op + " imm"
> eaCode = "EA = Base"
> if not post:
> eaCode += offset
> eaCode += ";"
>
> accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
> if writeback:
> accCode += "Base = Base %s;\n" % offset
> base = buildMemBase("MemoryNewImm", post, writeback)
>
> emitStore(name, Name, True, eaCode, accCode, [], [], base)
>
> def buildDoubleRegStore(mnem, post, add, writeback):
> name = mnem
> Name = storeDoubleRegClassName(post, add, writeback)
>
> if add:
> op = " +"
> else:
> op = " -"
>
> offset = op + " shift_rm_imm(Index, shiftAmt," + \
> " shiftType, CondCodes<29:>)"
> eaCode = "EA = Base"
> if not post:
> eaCode += offset
> eaCode += ";"
>
> accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
> if writeback:
> accCode += "Base = Base %s;\n" % offset
> base = buildMemBase("MemoryNewReg", post, writeback)
>
> emitStore(name, Name, False, eaCode, accCode, [], [], base)
>
132a186,199
> def buildDoubleStores(mnem):
> buildDoubleImmStore(mnem, True, True, True)
> buildDoubleRegStore(mnem, True, True, True)
> buildDoubleImmStore(mnem, True, False, True)
> buildDoubleRegStore(mnem, True, False, True)
> buildDoubleImmStore(mnem, False, True, True)
> buildDoubleRegStore(mnem, False, True, True)
> buildDoubleImmStore(mnem, False, False, True)
> buildDoubleRegStore(mnem, False, False, True)
> buildDoubleImmStore(mnem, False, True, False)
> buildDoubleRegStore(mnem, False, True, False)
> buildDoubleImmStore(mnem, False, False, False)
> buildDoubleRegStore(mnem, False, False, False)
>
138a206,207
>
> buildDoubleStores("strd")