80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class SrsInst(LoadStoreInst):
86 execBase = 'Store'
87 decConstBase = 'Srs'
88
89 def __init__(self, mnem, post, add, writeback):
90 super(SrsInst, self).__init__()
91 self.name = mnem
92 self.post = post
93 self.add = add
94 self.writeback = writeback
95
96 self.Name = "SRS_" + storeImmClassName(post, add, writeback, 8)
97
98 def emit(self):
99 offset = 0
100 if self.post != self.add:
101 offset += 4
102 if not self.add:
103 offset -= 8
104
105 eaCode = "EA = SpMode + %d;" % offset
106
107 wbDiff = -8
108 if self.add:
109 wbDiff = 8
110 accCode = '''
111 CPSR cpsr = Cpsr;
112 Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
113 ((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
114 '''
115
116 global header_output, decoder_output, exec_output
117
118 codeBlobs = { "ea_code": eaCode,
119 "memacc_code": accCode,
120 "postacc_code": "" }
121 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
122
123 wbDecl = None
124 if self.writeback:
125 wbDecl = '''MicroAddiUop(machInst,
126 intRegInMode((OperatingMode)regMode, INTREG_SP),
127 intRegInMode((OperatingMode)regMode, INTREG_SP),
128 %d);''' % wbDiff
129
130 (newHeader,
131 newDecoder,
132 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
133 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
134 'SrsOp', wbDecl)
135
136 header_output += newHeader
137 decoder_output += newDecoder
138 exec_output += newExec
139
140 class StoreImmInst(StoreInst):
141 def __init__(self, *args, **kargs):
142 super(StoreImmInst, self).__init__(*args, **kargs)
143 self.offset = self.op + " imm"
144
145 if self.add:
146 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
147 else:
148 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
149
150 class StoreRegInst(StoreInst):
151 def __init__(self, *args, **kargs):
152 super(StoreRegInst, self).__init__(*args, **kargs)
153 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
154 " shiftType, CondCodes<29:>)"
155 if self.add:
156 self.wbDecl = '''
157 MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
158 '''
159 else:
160 self.wbDecl = '''
161 MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
162 '''
163
164 class StoreSingle(StoreInst):
165 def __init__(self, *args, **kargs):
166 super(StoreSingle, self).__init__(*args, **kargs)
167
168 # Build the default class name
169 self.Name = self.nameFunc(self.post, self.add, self.writeback,
170 self.size, self.sign, self.user)
171
172 # Add memory request flags where necessary
173 self.memFlags.append("%d" % (self.size - 1))
174 if self.user:
175 self.memFlags.append("ArmISA::TLB::UserMode")
176
177 if self.flavor == "exclusive":
178 self.memFlags.append("Request::LLSC")
179 elif self.flavor != "fp":
180 self.memFlags.append("ArmISA::TLB::AllowUnaligned")
181
182 # Disambiguate the class name for different flavors of stores
183 if self.flavor != "normal":
184 self.Name = "%s_%s" % (self.name.upper(), self.Name)
185
186 def emit(self):
187 # Address computation
188 eaCode = "EA = Base"
189 if not self.post:
190 eaCode += self.offset
191 eaCode += ";"
192
193 if self.flavor == "fp":
194 eaCode += vfpEnabledCheckCode
195
196 self.codeBlobs["ea_code"] = eaCode
197
198 # Code that actually handles the access
199 if self.flavor == "fp":
200 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
201 else:
202 accCode = \
203 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
204 accCode = accCode % \
205 { "suffix" : buildMemSuffix(self.sign, self.size) }
206
207 self.codeBlobs["memacc_code"] = accCode
208
209 # Push it out to the output files
210 base = buildMemBase(self.basePrefix, self.post, self.writeback)
211 wbDecl = None
212 if self.writeback:
213 wbDecl = self.wbDecl
214 self.emitHelper(base, wbDecl)
215
216 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
217 return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
218
219 class StoreImmEx(StoreImmInst, StoreSingle):
220 execBase = 'StoreEx'
221 decConstBase = 'StoreExImm'
222 basePrefix = 'MemoryExImm'
223 nameFunc = staticmethod(storeImmClassName)
| 81
82 header_output += newHeader
83 decoder_output += newDecoder
84 exec_output += newExec
85
86 class SrsInst(LoadStoreInst):
87 execBase = 'Store'
88 decConstBase = 'Srs'
89
90 def __init__(self, mnem, post, add, writeback):
91 super(SrsInst, self).__init__()
92 self.name = mnem
93 self.post = post
94 self.add = add
95 self.writeback = writeback
96
97 self.Name = "SRS_" + storeImmClassName(post, add, writeback, 8)
98
99 def emit(self):
100 offset = 0
101 if self.post != self.add:
102 offset += 4
103 if not self.add:
104 offset -= 8
105
106 eaCode = "EA = SpMode + %d;" % offset
107
108 wbDiff = -8
109 if self.add:
110 wbDiff = 8
111 accCode = '''
112 CPSR cpsr = Cpsr;
113 Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
114 ((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
115 '''
116
117 global header_output, decoder_output, exec_output
118
119 codeBlobs = { "ea_code": eaCode,
120 "memacc_code": accCode,
121 "postacc_code": "" }
122 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
123
124 wbDecl = None
125 if self.writeback:
126 wbDecl = '''MicroAddiUop(machInst,
127 intRegInMode((OperatingMode)regMode, INTREG_SP),
128 intRegInMode((OperatingMode)regMode, INTREG_SP),
129 %d);''' % wbDiff
130
131 (newHeader,
132 newDecoder,
133 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
134 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
135 'SrsOp', wbDecl)
136
137 header_output += newHeader
138 decoder_output += newDecoder
139 exec_output += newExec
140
141 class StoreImmInst(StoreInst):
142 def __init__(self, *args, **kargs):
143 super(StoreImmInst, self).__init__(*args, **kargs)
144 self.offset = self.op + " imm"
145
146 if self.add:
147 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
148 else:
149 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
150
151 class StoreRegInst(StoreInst):
152 def __init__(self, *args, **kargs):
153 super(StoreRegInst, self).__init__(*args, **kargs)
154 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
155 " shiftType, CondCodes<29:>)"
156 if self.add:
157 self.wbDecl = '''
158 MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
159 '''
160 else:
161 self.wbDecl = '''
162 MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
163 '''
164
165 class StoreSingle(StoreInst):
166 def __init__(self, *args, **kargs):
167 super(StoreSingle, self).__init__(*args, **kargs)
168
169 # Build the default class name
170 self.Name = self.nameFunc(self.post, self.add, self.writeback,
171 self.size, self.sign, self.user)
172
173 # Add memory request flags where necessary
174 self.memFlags.append("%d" % (self.size - 1))
175 if self.user:
176 self.memFlags.append("ArmISA::TLB::UserMode")
177
178 if self.flavor == "exclusive":
179 self.memFlags.append("Request::LLSC")
180 elif self.flavor != "fp":
181 self.memFlags.append("ArmISA::TLB::AllowUnaligned")
182
183 # Disambiguate the class name for different flavors of stores
184 if self.flavor != "normal":
185 self.Name = "%s_%s" % (self.name.upper(), self.Name)
186
187 def emit(self):
188 # Address computation
189 eaCode = "EA = Base"
190 if not self.post:
191 eaCode += self.offset
192 eaCode += ";"
193
194 if self.flavor == "fp":
195 eaCode += vfpEnabledCheckCode
196
197 self.codeBlobs["ea_code"] = eaCode
198
199 # Code that actually handles the access
200 if self.flavor == "fp":
201 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
202 else:
203 accCode = \
204 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
205 accCode = accCode % \
206 { "suffix" : buildMemSuffix(self.sign, self.size) }
207
208 self.codeBlobs["memacc_code"] = accCode
209
210 # Push it out to the output files
211 base = buildMemBase(self.basePrefix, self.post, self.writeback)
212 wbDecl = None
213 if self.writeback:
214 wbDecl = self.wbDecl
215 self.emitHelper(base, wbDecl)
216
217 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
218 return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
219
220 class StoreImmEx(StoreImmInst, StoreSingle):
221 execBase = 'StoreEx'
222 decConstBase = 'StoreExImm'
223 basePrefix = 'MemoryExImm'
224 nameFunc = staticmethod(storeImmClassName)
|
224
225 def __init__(self, *args, **kargs):
226 super(StoreImmEx, self).__init__(*args, **kargs)
227 self.codeBlobs["postacc_code"] = "Result = !writeResult;"
228
229 class StoreImm(StoreImmInst, StoreSingle):
230 decConstBase = 'LoadStoreImm'
231 basePrefix = 'MemoryImm'
232 nameFunc = staticmethod(storeImmClassName)
233
234 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
235 return memClassName("STORE_REG", post, add, writeback, size, sign, user)
236
237 class StoreReg(StoreRegInst, StoreSingle):
238 decConstBase = 'StoreReg'
239 basePrefix = 'MemoryReg'
240 nameFunc = staticmethod(storeRegClassName)
241
242 class StoreDouble(StoreInst):
243 def __init__(self, *args, **kargs):
244 super(StoreDouble, self).__init__(*args, **kargs)
245
246 # Build the default class name
247 self.Name = self.nameFunc(self.post, self.add, self.writeback)
248
249 # Add memory request flags where necessary
250 if self.flavor == "exclusive":
251 self.memFlags.append("Request::LLSC")
252 self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
253 else:
254 self.memFlags.append("ArmISA::TLB::AlignWord")
255
256 # Disambiguate the class name for different flavors of stores
257 if self.flavor != "normal":
258 self.Name = "%s_%s" % (self.name.upper(), self.Name)
259
260 def emit(self):
261 # Address computation code
262 eaCode = "EA = Base"
263 if not self.post:
264 eaCode += self.offset
265 eaCode += ";"
266
267 if self.flavor == "fp":
268 eaCode += vfpEnabledCheckCode
269
270 self.codeBlobs["ea_code"] = eaCode
271
272 # Code that actually handles the access
273 if self.flavor == "fp":
274 accCode = '''
275 uint64_t swappedMem = (uint64_t)FpDest.uw |
276 ((uint64_t)FpDest2.uw << 32);
277 Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
278 '''
279 else:
280 accCode = '''
281 CPSR cpsr = Cpsr;
282 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
283 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
284 '''
285
286 self.codeBlobs["memacc_code"] = accCode
287
288 # Push it out to the output files
289 base = buildMemBase(self.basePrefix, self.post, self.writeback)
290 wbDecl = None
291 if self.writeback:
292 wbDecl = self.wbDecl
293 self.emitHelper(base, wbDecl)
294
295 def storeDoubleImmClassName(post, add, writeback):
296 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
297
298 class StoreDoubleImmEx(StoreImmInst, StoreDouble):
299 execBase = 'StoreEx'
300 decConstBase = 'StoreExDImm'
301 basePrefix = 'MemoryExDImm'
302 nameFunc = staticmethod(storeDoubleImmClassName)
| 226
227 def __init__(self, *args, **kargs):
228 super(StoreImmEx, self).__init__(*args, **kargs)
229 self.codeBlobs["postacc_code"] = "Result = !writeResult;"
230
231 class StoreImm(StoreImmInst, StoreSingle):
232 decConstBase = 'LoadStoreImm'
233 basePrefix = 'MemoryImm'
234 nameFunc = staticmethod(storeImmClassName)
235
236 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
237 return memClassName("STORE_REG", post, add, writeback, size, sign, user)
238
239 class StoreReg(StoreRegInst, StoreSingle):
240 decConstBase = 'StoreReg'
241 basePrefix = 'MemoryReg'
242 nameFunc = staticmethod(storeRegClassName)
243
244 class StoreDouble(StoreInst):
245 def __init__(self, *args, **kargs):
246 super(StoreDouble, self).__init__(*args, **kargs)
247
248 # Build the default class name
249 self.Name = self.nameFunc(self.post, self.add, self.writeback)
250
251 # Add memory request flags where necessary
252 if self.flavor == "exclusive":
253 self.memFlags.append("Request::LLSC")
254 self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
255 else:
256 self.memFlags.append("ArmISA::TLB::AlignWord")
257
258 # Disambiguate the class name for different flavors of stores
259 if self.flavor != "normal":
260 self.Name = "%s_%s" % (self.name.upper(), self.Name)
261
262 def emit(self):
263 # Address computation code
264 eaCode = "EA = Base"
265 if not self.post:
266 eaCode += self.offset
267 eaCode += ";"
268
269 if self.flavor == "fp":
270 eaCode += vfpEnabledCheckCode
271
272 self.codeBlobs["ea_code"] = eaCode
273
274 # Code that actually handles the access
275 if self.flavor == "fp":
276 accCode = '''
277 uint64_t swappedMem = (uint64_t)FpDest.uw |
278 ((uint64_t)FpDest2.uw << 32);
279 Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
280 '''
281 else:
282 accCode = '''
283 CPSR cpsr = Cpsr;
284 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
285 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
286 '''
287
288 self.codeBlobs["memacc_code"] = accCode
289
290 # Push it out to the output files
291 base = buildMemBase(self.basePrefix, self.post, self.writeback)
292 wbDecl = None
293 if self.writeback:
294 wbDecl = self.wbDecl
295 self.emitHelper(base, wbDecl)
296
297 def storeDoubleImmClassName(post, add, writeback):
298 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
299
300 class StoreDoubleImmEx(StoreImmInst, StoreDouble):
301 execBase = 'StoreEx'
302 decConstBase = 'StoreExDImm'
303 basePrefix = 'MemoryExDImm'
304 nameFunc = staticmethod(storeDoubleImmClassName)
|
303
304 def __init__(self, *args, **kargs):
305 super(StoreDoubleImmEx, self).__init__(*args, **kargs)
306 self.codeBlobs["postacc_code"] = "Result = !writeResult;"
307
308 class StoreDoubleImm(StoreImmInst, StoreDouble):
309 decConstBase = 'LoadStoreDImm'
310 basePrefix = 'MemoryDImm'
311 nameFunc = staticmethod(storeDoubleImmClassName)
312
313 def storeDoubleRegClassName(post, add, writeback):
314 return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
315
316 class StoreDoubleReg(StoreRegInst, StoreDouble):
317 decConstBase = 'StoreDReg'
318 basePrefix = 'MemoryDReg'
319 nameFunc = staticmethod(storeDoubleRegClassName)
320
321 def buildStores(mnem, size=4, sign=False, user=False):
322 StoreImm(mnem, True, True, True, size, sign, user).emit()
323 StoreReg(mnem, True, True, True, size, sign, user).emit()
324 StoreImm(mnem, True, False, True, size, sign, user).emit()
325 StoreReg(mnem, True, False, True, size, sign, user).emit()
326 StoreImm(mnem, False, True, True, size, sign, user).emit()
327 StoreReg(mnem, False, True, True, size, sign, user).emit()
328 StoreImm(mnem, False, False, True, size, sign, user).emit()
329 StoreReg(mnem, False, False, True, size, sign, user).emit()
330 StoreImm(mnem, False, True, False, size, sign, user).emit()
331 StoreReg(mnem, False, True, False, size, sign, user).emit()
332 StoreImm(mnem, False, False, False, size, sign, user).emit()
333 StoreReg(mnem, False, False, False, size, sign, user).emit()
334
335 def buildDoubleStores(mnem):
336 StoreDoubleImm(mnem, True, True, True).emit()
337 StoreDoubleReg(mnem, True, True, True).emit()
338 StoreDoubleImm(mnem, True, False, True).emit()
339 StoreDoubleReg(mnem, True, False, True).emit()
340 StoreDoubleImm(mnem, False, True, True).emit()
341 StoreDoubleReg(mnem, False, True, True).emit()
342 StoreDoubleImm(mnem, False, False, True).emit()
343 StoreDoubleReg(mnem, False, False, True).emit()
344 StoreDoubleImm(mnem, False, True, False).emit()
345 StoreDoubleReg(mnem, False, True, False).emit()
346 StoreDoubleImm(mnem, False, False, False).emit()
347 StoreDoubleReg(mnem, False, False, False).emit()
348
349 def buildSrsStores(mnem):
350 SrsInst(mnem, True, True, True).emit()
351 SrsInst(mnem, True, True, False).emit()
352 SrsInst(mnem, True, False, True).emit()
353 SrsInst(mnem, True, False, False).emit()
354 SrsInst(mnem, False, True, True).emit()
355 SrsInst(mnem, False, True, False).emit()
356 SrsInst(mnem, False, False, True).emit()
357 SrsInst(mnem, False, False, False).emit()
358
359 buildStores("str")
360 buildStores("strt", user=True)
361 buildStores("strb", size=1)
362 buildStores("strbt", size=1, user=True)
363 buildStores("strh", size=2)
364 buildStores("strht", size=2, user=True)
365
366 buildSrsStores("srs")
367
368 buildDoubleStores("strd")
369
370 StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
371 StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
372 StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
373 StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
374
375 StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
376 StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
377 StoreDoubleImm("vstr", False, True, False, flavor="fp").emit()
378 StoreDoubleImm("vstr", False, False, False, flavor="fp").emit()
379}};
| 306
307 def __init__(self, *args, **kargs):
308 super(StoreDoubleImmEx, self).__init__(*args, **kargs)
309 self.codeBlobs["postacc_code"] = "Result = !writeResult;"
310
311 class StoreDoubleImm(StoreImmInst, StoreDouble):
312 decConstBase = 'LoadStoreDImm'
313 basePrefix = 'MemoryDImm'
314 nameFunc = staticmethod(storeDoubleImmClassName)
315
316 def storeDoubleRegClassName(post, add, writeback):
317 return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
318
319 class StoreDoubleReg(StoreRegInst, StoreDouble):
320 decConstBase = 'StoreDReg'
321 basePrefix = 'MemoryDReg'
322 nameFunc = staticmethod(storeDoubleRegClassName)
323
324 def buildStores(mnem, size=4, sign=False, user=False):
325 StoreImm(mnem, True, True, True, size, sign, user).emit()
326 StoreReg(mnem, True, True, True, size, sign, user).emit()
327 StoreImm(mnem, True, False, True, size, sign, user).emit()
328 StoreReg(mnem, True, False, True, size, sign, user).emit()
329 StoreImm(mnem, False, True, True, size, sign, user).emit()
330 StoreReg(mnem, False, True, True, size, sign, user).emit()
331 StoreImm(mnem, False, False, True, size, sign, user).emit()
332 StoreReg(mnem, False, False, True, size, sign, user).emit()
333 StoreImm(mnem, False, True, False, size, sign, user).emit()
334 StoreReg(mnem, False, True, False, size, sign, user).emit()
335 StoreImm(mnem, False, False, False, size, sign, user).emit()
336 StoreReg(mnem, False, False, False, size, sign, user).emit()
337
338 def buildDoubleStores(mnem):
339 StoreDoubleImm(mnem, True, True, True).emit()
340 StoreDoubleReg(mnem, True, True, True).emit()
341 StoreDoubleImm(mnem, True, False, True).emit()
342 StoreDoubleReg(mnem, True, False, True).emit()
343 StoreDoubleImm(mnem, False, True, True).emit()
344 StoreDoubleReg(mnem, False, True, True).emit()
345 StoreDoubleImm(mnem, False, False, True).emit()
346 StoreDoubleReg(mnem, False, False, True).emit()
347 StoreDoubleImm(mnem, False, True, False).emit()
348 StoreDoubleReg(mnem, False, True, False).emit()
349 StoreDoubleImm(mnem, False, False, False).emit()
350 StoreDoubleReg(mnem, False, False, False).emit()
351
352 def buildSrsStores(mnem):
353 SrsInst(mnem, True, True, True).emit()
354 SrsInst(mnem, True, True, False).emit()
355 SrsInst(mnem, True, False, True).emit()
356 SrsInst(mnem, True, False, False).emit()
357 SrsInst(mnem, False, True, True).emit()
358 SrsInst(mnem, False, True, False).emit()
359 SrsInst(mnem, False, False, True).emit()
360 SrsInst(mnem, False, False, False).emit()
361
362 buildStores("str")
363 buildStores("strt", user=True)
364 buildStores("strb", size=1)
365 buildStores("strbt", size=1, user=True)
366 buildStores("strh", size=2)
367 buildStores("strht", size=2, user=True)
368
369 buildSrsStores("srs")
370
371 buildDoubleStores("strd")
372
373 StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
374 StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
375 StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
376 StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
377
378 StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
379 StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
380 StoreDoubleImm("vstr", False, True, False, flavor="fp").emit()
381 StoreDoubleImm("vstr", False, False, False, flavor="fp").emit()
382}};
|