130 131 header_output += newHeader 132 decoder_output += newDecoder 133 exec_output += newExec 134 135 class StoreImmInst(StoreInst): 136 def __init__(self, *args, **kargs): 137 super(StoreImmInst, self).__init__(*args, **kargs) 138 self.offset = self.op + " imm" 139 140 if self.add: 141 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" 142 else: 143 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);" 144 145 class StoreRegInst(StoreInst): 146 def __init__(self, *args, **kargs): 147 super(StoreRegInst, self).__init__(*args, **kargs) 148 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 149 " shiftType, CondCodes<29:>)" 150 if self.add: 151 self.wbDecl = ''' 152 MicroAddUop(machInst, base, base, index, shiftAmt, shiftType); 153 ''' 154 else: 155 self.wbDecl = ''' 156 MicroSubUop(machInst, base, base, index, shiftAmt, shiftType); 157 ''' 158 159 class StoreSingle(StoreInst): 160 def __init__(self, *args, **kargs): 161 super(StoreSingle, self).__init__(*args, **kargs) 162 163 # Build the default class name 164 self.Name = self.nameFunc(self.post, self.add, self.writeback, 165 self.size, self.sign, self.user) 166 167 # Add memory request flags where necessary 168 self.memFlags.append("%d" % (self.size - 1)) 169 if self.user: 170 self.memFlags.append("ArmISA::TLB::UserMode") 171 172 if self.flavor == "exclusive": 173 self.memFlags.append("Request::LLSC") 174 elif self.flavor != "fp": 175 self.memFlags.append("ArmISA::TLB::AllowUnaligned") 176 177 # Disambiguate the class name for different flavors of stores 178 if self.flavor != "normal": 179 self.Name = "%s_%s" % (self.name.upper(), self.Name) 180 181 def emit(self): 182 # Address computation 183 eaCode = "EA = Base" 184 if not self.post: 185 eaCode += self.offset 186 eaCode += ";" 187 188 if self.flavor == "fp": 189 eaCode += vfpEnabledCheckCode 190 191 self.codeBlobs["ea_code"] = eaCode 192 193 # Code that actually handles the access 194 if self.flavor == "fp": 195 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);' 196 else: 197 accCode = \ 198 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);' 199 accCode = accCode % \ 200 { "suffix" : buildMemSuffix(self.sign, self.size) } 201 202 self.codeBlobs["memacc_code"] = accCode 203 204 # Push it out to the output files 205 base = buildMemBase(self.basePrefix, self.post, self.writeback) 206 wbDecl = None 207 if self.writeback: 208 wbDecl = self.wbDecl 209 self.emitHelper(base, wbDecl) 210 211 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False): 212 return memClassName("STORE_IMM", post, add, writeback, size, sign, user) 213 214 class StoreImmEx(StoreImmInst, StoreSingle): 215 execBase = 'StoreEx' 216 decConstBase = 'StoreExImm' 217 basePrefix = 'MemoryExImm' 218 nameFunc = staticmethod(storeImmClassName) 219 220 def __init__(self, *args, **kargs): 221 super(StoreImmEx, self).__init__(*args, **kargs) 222 self.codeBlobs["postacc_code"] = "Result = !writeResult;" 223 224 class StoreImm(StoreImmInst, StoreSingle): 225 decConstBase = 'LoadStoreImm' 226 basePrefix = 'MemoryImm' 227 nameFunc = staticmethod(storeImmClassName) 228 229 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False): 230 return memClassName("STORE_REG", post, add, writeback, size, sign, user) 231 232 class StoreReg(StoreRegInst, StoreSingle): 233 decConstBase = 'StoreReg' 234 basePrefix = 'MemoryReg' 235 nameFunc = staticmethod(storeRegClassName) 236 237 class StoreDouble(StoreInst): 238 def __init__(self, *args, **kargs): 239 super(StoreDouble, self).__init__(*args, **kargs) 240 241 # Build the default class name 242 self.Name = self.nameFunc(self.post, self.add, self.writeback) 243 244 # Add memory request flags where necessary 245 if self.flavor == "exclusive": 246 self.memFlags.append("Request::LLSC") 247 self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 248 else: 249 self.memFlags.append("ArmISA::TLB::AlignWord") 250 251 # Disambiguate the class name for different flavors of stores 252 if self.flavor != "normal": 253 self.Name = "%s_%s" % (self.name.upper(), self.Name) 254 255 def emit(self): 256 # Address computation code 257 eaCode = "EA = Base" 258 if not self.post: 259 eaCode += self.offset 260 eaCode += ";" 261 262 if self.flavor == "fp": 263 eaCode += vfpEnabledCheckCode 264 265 self.codeBlobs["ea_code"] = eaCode 266 267 # Code that actually handles the access 268 if self.flavor == "fp": 269 accCode = ''' 270 uint64_t swappedMem = (uint64_t)FpDest.uw | 271 ((uint64_t)FpDest2.uw << 32); 272 Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e); 273 ''' 274 else: 275 accCode = ''' 276 CPSR cpsr = Cpsr; 277 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 278 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 279 ''' 280 281 self.codeBlobs["memacc_code"] = accCode 282 283 # Push it out to the output files 284 base = buildMemBase(self.basePrefix, self.post, self.writeback) 285 wbDecl = None 286 if self.writeback: 287 wbDecl = self.wbDecl 288 self.emitHelper(base, wbDecl) 289 290 def storeDoubleImmClassName(post, add, writeback): 291 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False) 292 293 class StoreDoubleImmEx(StoreImmInst, StoreDouble): 294 execBase = 'StoreEx' 295 decConstBase = 'StoreExDImm' 296 basePrefix = 'MemoryExDImm' 297 nameFunc = staticmethod(storeDoubleImmClassName) 298 299 def __init__(self, *args, **kargs): 300 super(StoreDoubleImmEx, self).__init__(*args, **kargs) 301 self.codeBlobs["postacc_code"] = "Result = !writeResult;" 302 303 class StoreDoubleImm(StoreImmInst, StoreDouble): 304 decConstBase = 'LoadStoreDImm' 305 basePrefix = 'MemoryDImm' 306 nameFunc = staticmethod(storeDoubleImmClassName) 307 308 def storeDoubleRegClassName(post, add, writeback): 309 return memClassName("STORE_REGD", post, add, writeback, 4, False, False) 310 311 class StoreDoubleReg(StoreRegInst, StoreDouble): 312 decConstBase = 'StoreDReg' 313 basePrefix = 'MemoryDReg' 314 nameFunc = staticmethod(storeDoubleRegClassName) 315 316 def buildStores(mnem, size=4, sign=False, user=False): 317 StoreImm(mnem, True, True, True, size, sign, user).emit() 318 StoreReg(mnem, True, True, True, size, sign, user).emit() 319 StoreImm(mnem, True, False, True, size, sign, user).emit() 320 StoreReg(mnem, True, False, True, size, sign, user).emit() 321 StoreImm(mnem, False, True, True, size, sign, user).emit() 322 StoreReg(mnem, False, True, True, size, sign, user).emit() 323 StoreImm(mnem, False, False, True, size, sign, user).emit() 324 StoreReg(mnem, False, False, True, size, sign, user).emit() 325 StoreImm(mnem, False, True, False, size, sign, user).emit() 326 StoreReg(mnem, False, True, False, size, sign, user).emit() 327 StoreImm(mnem, False, False, False, size, sign, user).emit() 328 StoreReg(mnem, False, False, False, size, sign, user).emit() 329 330 def buildDoubleStores(mnem): 331 StoreDoubleImm(mnem, True, True, True).emit() 332 StoreDoubleReg(mnem, True, True, True).emit() 333 StoreDoubleImm(mnem, True, False, True).emit() 334 StoreDoubleReg(mnem, True, False, True).emit() 335 StoreDoubleImm(mnem, False, True, True).emit() 336 StoreDoubleReg(mnem, False, True, True).emit() 337 StoreDoubleImm(mnem, False, False, True).emit() 338 StoreDoubleReg(mnem, False, False, True).emit() 339 StoreDoubleImm(mnem, False, True, False).emit() 340 StoreDoubleReg(mnem, False, True, False).emit() 341 StoreDoubleImm(mnem, False, False, False).emit() 342 StoreDoubleReg(mnem, False, False, False).emit() 343 344 def buildSrsStores(mnem): 345 SrsInst(mnem, True, True, True).emit() 346 SrsInst(mnem, True, True, False).emit() 347 SrsInst(mnem, True, False, True).emit() 348 SrsInst(mnem, True, False, False).emit() 349 SrsInst(mnem, False, True, True).emit() 350 SrsInst(mnem, False, True, False).emit() 351 SrsInst(mnem, False, False, True).emit() 352 SrsInst(mnem, False, False, False).emit() 353 354 buildStores("str") 355 buildStores("strt", user=True) 356 buildStores("strb", size=1) 357 buildStores("strbt", size=1, user=True) 358 buildStores("strh", size=2) 359 buildStores("strht", size=2, user=True) 360 361 buildSrsStores("srs") 362 363 buildDoubleStores("strd") 364 365 StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit() 366 StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit() 367 StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit() 368 StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit() 369 370 StoreImm("vstr", False, True, False, size=4, flavor="fp").emit() 371 StoreImm("vstr", False, False, False, size=4, flavor="fp").emit() 372 StoreDoubleImm("vstr", False, True, False, flavor="fp").emit() 373 StoreDoubleImm("vstr", False, False, False, flavor="fp").emit() 374}};
| 135 136 header_output += newHeader 137 decoder_output += newDecoder 138 exec_output += newExec 139 140 class StoreImmInst(StoreInst): 141 def __init__(self, *args, **kargs): 142 super(StoreImmInst, self).__init__(*args, **kargs) 143 self.offset = self.op + " imm" 144 145 if self.add: 146 self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" 147 else: 148 self.wbDecl = "MicroSubiUop(machInst, base, base, imm);" 149 150 class StoreRegInst(StoreInst): 151 def __init__(self, *args, **kargs): 152 super(StoreRegInst, self).__init__(*args, **kargs) 153 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 154 " shiftType, CondCodes<29:>)" 155 if self.add: 156 self.wbDecl = ''' 157 MicroAddUop(machInst, base, base, index, shiftAmt, shiftType); 158 ''' 159 else: 160 self.wbDecl = ''' 161 MicroSubUop(machInst, base, base, index, shiftAmt, shiftType); 162 ''' 163 164 class StoreSingle(StoreInst): 165 def __init__(self, *args, **kargs): 166 super(StoreSingle, self).__init__(*args, **kargs) 167 168 # Build the default class name 169 self.Name = self.nameFunc(self.post, self.add, self.writeback, 170 self.size, self.sign, self.user) 171 172 # Add memory request flags where necessary 173 self.memFlags.append("%d" % (self.size - 1)) 174 if self.user: 175 self.memFlags.append("ArmISA::TLB::UserMode") 176 177 if self.flavor == "exclusive": 178 self.memFlags.append("Request::LLSC") 179 elif self.flavor != "fp": 180 self.memFlags.append("ArmISA::TLB::AllowUnaligned") 181 182 # Disambiguate the class name for different flavors of stores 183 if self.flavor != "normal": 184 self.Name = "%s_%s" % (self.name.upper(), self.Name) 185 186 def emit(self): 187 # Address computation 188 eaCode = "EA = Base" 189 if not self.post: 190 eaCode += self.offset 191 eaCode += ";" 192 193 if self.flavor == "fp": 194 eaCode += vfpEnabledCheckCode 195 196 self.codeBlobs["ea_code"] = eaCode 197 198 # Code that actually handles the access 199 if self.flavor == "fp": 200 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);' 201 else: 202 accCode = \ 203 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);' 204 accCode = accCode % \ 205 { "suffix" : buildMemSuffix(self.sign, self.size) } 206 207 self.codeBlobs["memacc_code"] = accCode 208 209 # Push it out to the output files 210 base = buildMemBase(self.basePrefix, self.post, self.writeback) 211 wbDecl = None 212 if self.writeback: 213 wbDecl = self.wbDecl 214 self.emitHelper(base, wbDecl) 215 216 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False): 217 return memClassName("STORE_IMM", post, add, writeback, size, sign, user) 218 219 class StoreImmEx(StoreImmInst, StoreSingle): 220 execBase = 'StoreEx' 221 decConstBase = 'StoreExImm' 222 basePrefix = 'MemoryExImm' 223 nameFunc = staticmethod(storeImmClassName) 224 225 def __init__(self, *args, **kargs): 226 super(StoreImmEx, self).__init__(*args, **kargs) 227 self.codeBlobs["postacc_code"] = "Result = !writeResult;" 228 229 class StoreImm(StoreImmInst, StoreSingle): 230 decConstBase = 'LoadStoreImm' 231 basePrefix = 'MemoryImm' 232 nameFunc = staticmethod(storeImmClassName) 233 234 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False): 235 return memClassName("STORE_REG", post, add, writeback, size, sign, user) 236 237 class StoreReg(StoreRegInst, StoreSingle): 238 decConstBase = 'StoreReg' 239 basePrefix = 'MemoryReg' 240 nameFunc = staticmethod(storeRegClassName) 241 242 class StoreDouble(StoreInst): 243 def __init__(self, *args, **kargs): 244 super(StoreDouble, self).__init__(*args, **kargs) 245 246 # Build the default class name 247 self.Name = self.nameFunc(self.post, self.add, self.writeback) 248 249 # Add memory request flags where necessary 250 if self.flavor == "exclusive": 251 self.memFlags.append("Request::LLSC") 252 self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 253 else: 254 self.memFlags.append("ArmISA::TLB::AlignWord") 255 256 # Disambiguate the class name for different flavors of stores 257 if self.flavor != "normal": 258 self.Name = "%s_%s" % (self.name.upper(), self.Name) 259 260 def emit(self): 261 # Address computation code 262 eaCode = "EA = Base" 263 if not self.post: 264 eaCode += self.offset 265 eaCode += ";" 266 267 if self.flavor == "fp": 268 eaCode += vfpEnabledCheckCode 269 270 self.codeBlobs["ea_code"] = eaCode 271 272 # Code that actually handles the access 273 if self.flavor == "fp": 274 accCode = ''' 275 uint64_t swappedMem = (uint64_t)FpDest.uw | 276 ((uint64_t)FpDest2.uw << 32); 277 Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e); 278 ''' 279 else: 280 accCode = ''' 281 CPSR cpsr = Cpsr; 282 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 283 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 284 ''' 285 286 self.codeBlobs["memacc_code"] = accCode 287 288 # Push it out to the output files 289 base = buildMemBase(self.basePrefix, self.post, self.writeback) 290 wbDecl = None 291 if self.writeback: 292 wbDecl = self.wbDecl 293 self.emitHelper(base, wbDecl) 294 295 def storeDoubleImmClassName(post, add, writeback): 296 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False) 297 298 class StoreDoubleImmEx(StoreImmInst, StoreDouble): 299 execBase = 'StoreEx' 300 decConstBase = 'StoreExDImm' 301 basePrefix = 'MemoryExDImm' 302 nameFunc = staticmethod(storeDoubleImmClassName) 303 304 def __init__(self, *args, **kargs): 305 super(StoreDoubleImmEx, self).__init__(*args, **kargs) 306 self.codeBlobs["postacc_code"] = "Result = !writeResult;" 307 308 class StoreDoubleImm(StoreImmInst, StoreDouble): 309 decConstBase = 'LoadStoreDImm' 310 basePrefix = 'MemoryDImm' 311 nameFunc = staticmethod(storeDoubleImmClassName) 312 313 def storeDoubleRegClassName(post, add, writeback): 314 return memClassName("STORE_REGD", post, add, writeback, 4, False, False) 315 316 class StoreDoubleReg(StoreRegInst, StoreDouble): 317 decConstBase = 'StoreDReg' 318 basePrefix = 'MemoryDReg' 319 nameFunc = staticmethod(storeDoubleRegClassName) 320 321 def buildStores(mnem, size=4, sign=False, user=False): 322 StoreImm(mnem, True, True, True, size, sign, user).emit() 323 StoreReg(mnem, True, True, True, size, sign, user).emit() 324 StoreImm(mnem, True, False, True, size, sign, user).emit() 325 StoreReg(mnem, True, False, True, size, sign, user).emit() 326 StoreImm(mnem, False, True, True, size, sign, user).emit() 327 StoreReg(mnem, False, True, True, size, sign, user).emit() 328 StoreImm(mnem, False, False, True, size, sign, user).emit() 329 StoreReg(mnem, False, False, True, size, sign, user).emit() 330 StoreImm(mnem, False, True, False, size, sign, user).emit() 331 StoreReg(mnem, False, True, False, size, sign, user).emit() 332 StoreImm(mnem, False, False, False, size, sign, user).emit() 333 StoreReg(mnem, False, False, False, size, sign, user).emit() 334 335 def buildDoubleStores(mnem): 336 StoreDoubleImm(mnem, True, True, True).emit() 337 StoreDoubleReg(mnem, True, True, True).emit() 338 StoreDoubleImm(mnem, True, False, True).emit() 339 StoreDoubleReg(mnem, True, False, True).emit() 340 StoreDoubleImm(mnem, False, True, True).emit() 341 StoreDoubleReg(mnem, False, True, True).emit() 342 StoreDoubleImm(mnem, False, False, True).emit() 343 StoreDoubleReg(mnem, False, False, True).emit() 344 StoreDoubleImm(mnem, False, True, False).emit() 345 StoreDoubleReg(mnem, False, True, False).emit() 346 StoreDoubleImm(mnem, False, False, False).emit() 347 StoreDoubleReg(mnem, False, False, False).emit() 348 349 def buildSrsStores(mnem): 350 SrsInst(mnem, True, True, True).emit() 351 SrsInst(mnem, True, True, False).emit() 352 SrsInst(mnem, True, False, True).emit() 353 SrsInst(mnem, True, False, False).emit() 354 SrsInst(mnem, False, True, True).emit() 355 SrsInst(mnem, False, True, False).emit() 356 SrsInst(mnem, False, False, True).emit() 357 SrsInst(mnem, False, False, False).emit() 358 359 buildStores("str") 360 buildStores("strt", user=True) 361 buildStores("strb", size=1) 362 buildStores("strbt", size=1, user=True) 363 buildStores("strh", size=2) 364 buildStores("strht", size=2, user=True) 365 366 buildSrsStores("srs") 367 368 buildDoubleStores("strd") 369 370 StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit() 371 StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit() 372 StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit() 373 StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit() 374 375 StoreImm("vstr", False, True, False, size=4, flavor="fp").emit() 376 StoreImm("vstr", False, False, False, size=4, flavor="fp").emit() 377 StoreDoubleImm("vstr", False, True, False, flavor="fp").emit() 378 StoreDoubleImm("vstr", False, False, False, flavor="fp").emit() 379}};
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