1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 def storeImmClassName(post, add, writeback, \
47 size=4, sign=False, user=False):
48 return memClassName("STORE_IMM", post, add, writeback,
49 size, sign, user)
50
51 def storeRegClassName(post, add, writeback, \
52 size=4, sign=False, user=False):
53 return memClassName("STORE_REG", post, add, writeback,
54 size, sign, user)
55
56 def storeDoubleImmClassName(post, add, writeback):
57 return memClassName("STORE_IMMD", post, add, writeback,
58 4, False, False)
59
60 def storeDoubleRegClassName(post, add, writeback):
61 return memClassName("STORE_REGD", post, add, writeback,
62 4, False, False)
63
64 def emitStore(name, Name, imm, eaCode, accCode, \
65 memFlags, instFlags, base, double=False):
66 global header_output, decoder_output, exec_output
67
68 (newHeader,
69 newDecoder,
70 newExec) = loadStoreBase(name, Name, imm,
71 eaCode, accCode,
72 memFlags, instFlags, double,
73 base, execTemplateBase = 'Store')
74
75 header_output += newHeader
76 decoder_output += newDecoder
77 exec_output += newExec
78
79 def buildImmStore(mnem, post, add, writeback, \
80 size=4, sign=False, user=False):
81 name = mnem
82 Name = storeImmClassName(post, add, writeback, \
83 size, sign, user)
84
85 if add:
86 op = " +"
87 else:
88 op = " -"
89
90 offset = op + " imm"
91 eaCode = "EA = Base"
92 if not post:
93 eaCode += offset
94 eaCode += ";"
95
96 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
97 if writeback:
98 accCode += "Base = Base %s;\n" % offset
99 base = buildMemBase("MemoryImm", post, writeback)
100
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 def storeImmClassName(post, add, writeback, \
47 size=4, sign=False, user=False):
48 return memClassName("STORE_IMM", post, add, writeback,
49 size, sign, user)
50
51 def storeRegClassName(post, add, writeback, \
52 size=4, sign=False, user=False):
53 return memClassName("STORE_REG", post, add, writeback,
54 size, sign, user)
55
56 def storeDoubleImmClassName(post, add, writeback):
57 return memClassName("STORE_IMMD", post, add, writeback,
58 4, False, False)
59
60 def storeDoubleRegClassName(post, add, writeback):
61 return memClassName("STORE_REGD", post, add, writeback,
62 4, False, False)
63
64 def emitStore(name, Name, imm, eaCode, accCode, \
65 memFlags, instFlags, base, double=False):
66 global header_output, decoder_output, exec_output
67
68 (newHeader,
69 newDecoder,
70 newExec) = loadStoreBase(name, Name, imm,
71 eaCode, accCode,
72 memFlags, instFlags, double,
73 base, execTemplateBase = 'Store')
74
75 header_output += newHeader
76 decoder_output += newDecoder
77 exec_output += newExec
78
79 def buildImmStore(mnem, post, add, writeback, \
80 size=4, sign=False, user=False):
81 name = mnem
82 Name = storeImmClassName(post, add, writeback, \
83 size, sign, user)
84
85 if add:
86 op = " +"
87 else:
88 op = " -"
89
90 offset = op + " imm"
91 eaCode = "EA = Base"
92 if not post:
93 eaCode += offset
94 eaCode += ";"
95
96 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
97 if writeback:
98 accCode += "Base = Base %s;\n" % offset
99 base = buildMemBase("MemoryImm", post, writeback)
100
|
101 emitStore(name, Name, True, eaCode, accCode, [], [], base)
| 101 emitStore(name, Name, True, eaCode, accCode, \
102 ["ArmISA::TLB::MustBeOne", \
103 "ArmISA::TLB::AllowUnaligned", \
104 "%d" % (size - 1)], [], base)
|
102
103 def buildRegStore(mnem, post, add, writeback, \
104 size=4, sign=False, user=False):
105 name = mnem
106 Name = storeRegClassName(post, add, writeback,
107 size, sign, user)
108
109 if add:
110 op = " +"
111 else:
112 op = " -"
113
114 offset = op + " shift_rm_imm(Index, shiftAmt," + \
115 " shiftType, CondCodes<29:>)"
116 eaCode = "EA = Base"
117 if not post:
118 eaCode += offset
119 eaCode += ";"
120
121 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
122 if writeback:
123 accCode += "Base = Base %s;\n" % offset
124 base = buildMemBase("MemoryReg", post, writeback)
125
| 105
106 def buildRegStore(mnem, post, add, writeback, \
107 size=4, sign=False, user=False):
108 name = mnem
109 Name = storeRegClassName(post, add, writeback,
110 size, sign, user)
111
112 if add:
113 op = " +"
114 else:
115 op = " -"
116
117 offset = op + " shift_rm_imm(Index, shiftAmt," + \
118 " shiftType, CondCodes<29:>)"
119 eaCode = "EA = Base"
120 if not post:
121 eaCode += offset
122 eaCode += ";"
123
124 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
125 if writeback:
126 accCode += "Base = Base %s;\n" % offset
127 base = buildMemBase("MemoryReg", post, writeback)
128
|
126 emitStore(name, Name, False, eaCode, accCode, [], [], base)
| 129 emitStore(name, Name, False, eaCode, accCode, \
130 ["ArmISA::TLB::MustBeOne", \
131 "ArmISA::TLB::AllowUnaligned", \
132 "%d" % (size - 1)], [], base)
|
127
128 def buildDoubleImmStore(mnem, post, add, writeback):
129 name = mnem
130 Name = storeDoubleImmClassName(post, add, writeback)
131
132 if add:
133 op = " +"
134 else:
135 op = " -"
136
137 offset = op + " imm"
138 eaCode = "EA = Base"
139 if not post:
140 eaCode += offset
141 eaCode += ";"
142
143 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
144 if writeback:
145 accCode += "Base = Base %s;\n" % offset
146 base = buildMemBase("MemoryDImm", post, writeback)
147
148 emitStore(name, Name, True, eaCode, accCode, \
| 133
134 def buildDoubleImmStore(mnem, post, add, writeback):
135 name = mnem
136 Name = storeDoubleImmClassName(post, add, writeback)
137
138 if add:
139 op = " +"
140 else:
141 op = " -"
142
143 offset = op + " imm"
144 eaCode = "EA = Base"
145 if not post:
146 eaCode += offset
147 eaCode += ";"
148
149 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
150 if writeback:
151 accCode += "Base = Base %s;\n" % offset
152 base = buildMemBase("MemoryDImm", post, writeback)
153
154 emitStore(name, Name, True, eaCode, accCode, \
|
149 [], [], base, double=True)
| 155 ["ArmISA::TLB::MustBeOne",
156 "ArmISA::TLB::AlignWord"], [], base, double=True)
|
150
151 def buildDoubleRegStore(mnem, post, add, writeback):
152 name = mnem
153 Name = storeDoubleRegClassName(post, add, writeback)
154
155 if add:
156 op = " +"
157 else:
158 op = " -"
159
160 offset = op + " shift_rm_imm(Index, shiftAmt," + \
161 " shiftType, CondCodes<29:>)"
162 eaCode = "EA = Base"
163 if not post:
164 eaCode += offset
165 eaCode += ";"
166
167 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
168 if writeback:
169 accCode += "Base = Base %s;\n" % offset
170 base = buildMemBase("MemoryDReg", post, writeback)
171
172 emitStore(name, Name, False, eaCode, accCode, \
| 157
158 def buildDoubleRegStore(mnem, post, add, writeback):
159 name = mnem
160 Name = storeDoubleRegClassName(post, add, writeback)
161
162 if add:
163 op = " +"
164 else:
165 op = " -"
166
167 offset = op + " shift_rm_imm(Index, shiftAmt," + \
168 " shiftType, CondCodes<29:>)"
169 eaCode = "EA = Base"
170 if not post:
171 eaCode += offset
172 eaCode += ";"
173
174 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
175 if writeback:
176 accCode += "Base = Base %s;\n" % offset
177 base = buildMemBase("MemoryDReg", post, writeback)
178
179 emitStore(name, Name, False, eaCode, accCode, \
|
173 [], [], base, double=True)
| 180 ["ArmISA::TLB::MustBeOne", \
181 "ArmISA::TLB::AlignWord"], [], base, double=True)
|
174
175 def buildStores(mnem, size=4, sign=False, user=False):
176 buildImmStore(mnem, True, True, True, size, sign, user)
177 buildRegStore(mnem, True, True, True, size, sign, user)
178 buildImmStore(mnem, True, False, True, size, sign, user)
179 buildRegStore(mnem, True, False, True, size, sign, user)
180 buildImmStore(mnem, False, True, True, size, sign, user)
181 buildRegStore(mnem, False, True, True, size, sign, user)
182 buildImmStore(mnem, False, False, True, size, sign, user)
183 buildRegStore(mnem, False, False, True, size, sign, user)
184 buildImmStore(mnem, False, True, False, size, sign, user)
185 buildRegStore(mnem, False, True, False, size, sign, user)
186 buildImmStore(mnem, False, False, False, size, sign, user)
187 buildRegStore(mnem, False, False, False, size, sign, user)
188
189 def buildDoubleStores(mnem):
190 buildDoubleImmStore(mnem, True, True, True)
191 buildDoubleRegStore(mnem, True, True, True)
192 buildDoubleImmStore(mnem, True, False, True)
193 buildDoubleRegStore(mnem, True, False, True)
194 buildDoubleImmStore(mnem, False, True, True)
195 buildDoubleRegStore(mnem, False, True, True)
196 buildDoubleImmStore(mnem, False, False, True)
197 buildDoubleRegStore(mnem, False, False, True)
198 buildDoubleImmStore(mnem, False, True, False)
199 buildDoubleRegStore(mnem, False, True, False)
200 buildDoubleImmStore(mnem, False, False, False)
201 buildDoubleRegStore(mnem, False, False, False)
202
203 buildStores("str")
204 buildStores("strt", user=True)
205 buildStores("strb", size=1)
206 buildStores("strbt", size=1, user=True)
207 buildStores("strh", size=2)
208 buildStores("strht", size=2, user=True)
209
210 buildDoubleStores("strd")
211}};
| 182
183 def buildStores(mnem, size=4, sign=False, user=False):
184 buildImmStore(mnem, True, True, True, size, sign, user)
185 buildRegStore(mnem, True, True, True, size, sign, user)
186 buildImmStore(mnem, True, False, True, size, sign, user)
187 buildRegStore(mnem, True, False, True, size, sign, user)
188 buildImmStore(mnem, False, True, True, size, sign, user)
189 buildRegStore(mnem, False, True, True, size, sign, user)
190 buildImmStore(mnem, False, False, True, size, sign, user)
191 buildRegStore(mnem, False, False, True, size, sign, user)
192 buildImmStore(mnem, False, True, False, size, sign, user)
193 buildRegStore(mnem, False, True, False, size, sign, user)
194 buildImmStore(mnem, False, False, False, size, sign, user)
195 buildRegStore(mnem, False, False, False, size, sign, user)
196
197 def buildDoubleStores(mnem):
198 buildDoubleImmStore(mnem, True, True, True)
199 buildDoubleRegStore(mnem, True, True, True)
200 buildDoubleImmStore(mnem, True, False, True)
201 buildDoubleRegStore(mnem, True, False, True)
202 buildDoubleImmStore(mnem, False, True, True)
203 buildDoubleRegStore(mnem, False, True, True)
204 buildDoubleImmStore(mnem, False, False, True)
205 buildDoubleRegStore(mnem, False, False, True)
206 buildDoubleImmStore(mnem, False, True, False)
207 buildDoubleRegStore(mnem, False, True, False)
208 buildDoubleImmStore(mnem, False, False, False)
209 buildDoubleRegStore(mnem, False, False, False)
210
211 buildStores("str")
212 buildStores("strt", user=True)
213 buildStores("strb", size=1)
214 buildStores("strbt", size=1, user=True)
215 buildStores("strh", size=2)
216 buildStores("strht", size=2, user=True)
217
218 buildDoubleStores("strd")
219}};
|