str.isa (7296:27c60324ec4d) | str.isa (7303:6b70985664c8) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 47 unchanged lines hidden (view full) --- 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 47 unchanged lines hidden (view full) --- 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 |
64 def emitStore(name, Name, imm, eaCode, accCode, \ 65 memFlags, instFlags, base, double=False): | 64 def emitStore(name, Name, imm, eaCode, accCode, postAccCode, \ 65 memFlags, instFlags, base, double=False, strex=False, 66 execTemplateBase = 'Store'): |
66 global header_output, decoder_output, exec_output 67 68 (newHeader, 69 newDecoder, 70 newExec) = loadStoreBase(name, Name, imm, | 67 global header_output, decoder_output, exec_output 68 69 (newHeader, 70 newDecoder, 71 newExec) = loadStoreBase(name, Name, imm, |
71 eaCode, accCode, 72 memFlags, instFlags, double, 73 base, execTemplateBase = 'Store') | 72 eaCode, accCode, postAccCode, 73 memFlags, instFlags, double, strex, 74 base, execTemplateBase = execTemplateBase) |
74 75 header_output += newHeader 76 decoder_output += newDecoder 77 exec_output += newExec 78 79 def buildImmStore(mnem, post, add, writeback, \ | 75 76 header_output += newHeader 77 decoder_output += newDecoder 78 exec_output += newExec 79 80 def buildImmStore(mnem, post, add, writeback, \ |
80 size=4, sign=False, user=False): | 81 size=4, sign=False, user=False, strex=False): |
81 name = mnem 82 Name = storeImmClassName(post, add, writeback, \ 83 size, sign, user) 84 85 if add: 86 op = " +" 87 else: 88 op = " -" 89 90 offset = op + " imm" 91 eaCode = "EA = Base" 92 if not post: 93 eaCode += offset 94 eaCode += ";" 95 96 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 97 { "suffix" : buildMemSuffix(sign, size) } 98 if writeback: 99 accCode += "Base = Base %s;\n" % offset | 82 name = mnem 83 Name = storeImmClassName(post, add, writeback, \ 84 size, sign, user) 85 86 if add: 87 op = " +" 88 else: 89 op = " -" 90 91 offset = op + " imm" 92 eaCode = "EA = Base" 93 if not post: 94 eaCode += offset 95 eaCode += ";" 96 97 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 98 { "suffix" : buildMemSuffix(sign, size) } 99 if writeback: 100 accCode += "Base = Base %s;\n" % offset |
100 base = buildMemBase("MemoryImm", post, writeback) | |
101 | 101 |
102 emitStore(name, Name, True, eaCode, accCode, \ 103 ["ArmISA::TLB::MustBeOne", \ 104 "ArmISA::TLB::AllowUnaligned", \ 105 "%d" % (size - 1)], [], base) | 102 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] 103 if strex: 104 memFlags.append("Request::LLSC") 105 Name = "%s_%s" % (mnem.upper(), Name) 106 base = buildMemBase("MemoryExImm", post, writeback) 107 postAccCode = "Result = !writeResult;" 108 execTemplateBase = 'StoreEx' 109 else: 110 memFlags.append("ArmISA::TLB::AllowUnaligned") 111 base = buildMemBase("MemoryImm", post, writeback) 112 postAccCode = "" 113 execTemplateBase = 'Store' |
106 | 114 |
115 emitStore(name, Name, True, eaCode, accCode, postAccCode, \ 116 memFlags, [], base, strex=strex, 117 execTemplateBase = execTemplateBase) 118 |
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107 def buildRegStore(mnem, post, add, writeback, \ | 119 def buildRegStore(mnem, post, add, writeback, \ |
108 size=4, sign=False, user=False): | 120 size=4, sign=False, user=False, strex=False): |
109 name = mnem 110 Name = storeRegClassName(post, add, writeback, 111 size, sign, user) 112 113 if add: 114 op = " +" 115 else: 116 op = " -" --- 6 unchanged lines hidden (view full) --- 123 eaCode += ";" 124 125 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 126 { "suffix" : buildMemSuffix(sign, size) } 127 if writeback: 128 accCode += "Base = Base %s;\n" % offset 129 base = buildMemBase("MemoryReg", post, writeback) 130 | 121 name = mnem 122 Name = storeRegClassName(post, add, writeback, 123 size, sign, user) 124 125 if add: 126 op = " +" 127 else: 128 op = " -" --- 6 unchanged lines hidden (view full) --- 135 eaCode += ";" 136 137 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 138 { "suffix" : buildMemSuffix(sign, size) } 139 if writeback: 140 accCode += "Base = Base %s;\n" % offset 141 base = buildMemBase("MemoryReg", post, writeback) 142 |
131 emitStore(name, Name, False, eaCode, accCode, \ | 143 emitStore(name, Name, False, eaCode, accCode, "",\ |
132 ["ArmISA::TLB::MustBeOne", \ 133 "ArmISA::TLB::AllowUnaligned", \ 134 "%d" % (size - 1)], [], base) 135 | 144 ["ArmISA::TLB::MustBeOne", \ 145 "ArmISA::TLB::AllowUnaligned", \ 146 "%d" % (size - 1)], [], base) 147 |
136 def buildDoubleImmStore(mnem, post, add, writeback): | 148 def buildDoubleImmStore(mnem, post, add, writeback, strex=False): |
137 name = mnem 138 Name = storeDoubleImmClassName(post, add, writeback) 139 140 if add: 141 op = " +" 142 else: 143 op = " -" 144 --- 5 unchanged lines hidden (view full) --- 150 151 accCode = ''' 152 CPSR cpsr = Cpsr; 153 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 154 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 155 ''' 156 if writeback: 157 accCode += "Base = Base %s;\n" % offset | 149 name = mnem 150 Name = storeDoubleImmClassName(post, add, writeback) 151 152 if add: 153 op = " +" 154 else: 155 op = " -" 156 --- 5 unchanged lines hidden (view full) --- 162 163 accCode = ''' 164 CPSR cpsr = Cpsr; 165 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 166 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 167 ''' 168 if writeback: 169 accCode += "Base = Base %s;\n" % offset |
158 base = buildMemBase("MemoryDImm", post, writeback) | |
159 | 170 |
160 emitStore(name, Name, True, eaCode, accCode, \ 161 ["ArmISA::TLB::MustBeOne", 162 "ArmISA::TLB::AlignWord"], [], base, double=True) | 171 memFlags = ["ArmISA::TLB::MustBeOne", 172 "ArmISA::TLB::AlignWord"] 173 if strex: 174 memFlags.append("Request::LLSC") 175 Name = "%s_%s" % (mnem.upper(), Name) 176 base = buildMemBase("MemoryExDImm", post, writeback) 177 postAccCode = "Result = !writeResult;" 178 else: 179 base = buildMemBase("MemoryDImm", post, writeback) 180 postAccCode = "" |
163 | 181 |
182 emitStore(name, Name, True, eaCode, accCode, postAccCode, \ 183 memFlags, [], base, double=True, strex=strex) 184 |
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164 def buildDoubleRegStore(mnem, post, add, writeback): 165 name = mnem 166 Name = storeDoubleRegClassName(post, add, writeback) 167 168 if add: 169 op = " +" 170 else: 171 op = " -" --- 9 unchanged lines hidden (view full) --- 181 CPSR cpsr = Cpsr; 182 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 183 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 184 ''' 185 if writeback: 186 accCode += "Base = Base %s;\n" % offset 187 base = buildMemBase("MemoryDReg", post, writeback) 188 | 185 def buildDoubleRegStore(mnem, post, add, writeback): 186 name = mnem 187 Name = storeDoubleRegClassName(post, add, writeback) 188 189 if add: 190 op = " +" 191 else: 192 op = " -" --- 9 unchanged lines hidden (view full) --- 202 CPSR cpsr = Cpsr; 203 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 204 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 205 ''' 206 if writeback: 207 accCode += "Base = Base %s;\n" % offset 208 base = buildMemBase("MemoryDReg", post, writeback) 209 |
189 emitStore(name, Name, False, eaCode, accCode, \ 190 ["ArmISA::TLB::MustBeOne", \ 191 "ArmISA::TLB::AlignWord"], [], base, double=True) | 210 memFlags = ["ArmISA::TLB::MustBeOne", 211 "ArmISA::TLB::AlignWord"] |
192 | 212 |
213 emitStore(name, Name, False, eaCode, accCode, "", \ 214 memFlags, [], base, double=True) 215 |
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193 def buildStores(mnem, size=4, sign=False, user=False): 194 buildImmStore(mnem, True, True, True, size, sign, user) 195 buildRegStore(mnem, True, True, True, size, sign, user) 196 buildImmStore(mnem, True, False, True, size, sign, user) 197 buildRegStore(mnem, True, False, True, size, sign, user) 198 buildImmStore(mnem, False, True, True, size, sign, user) 199 buildRegStore(mnem, False, True, True, size, sign, user) 200 buildImmStore(mnem, False, False, True, size, sign, user) --- 20 unchanged lines hidden (view full) --- 221 buildStores("str") 222 buildStores("strt", user=True) 223 buildStores("strb", size=1) 224 buildStores("strbt", size=1, user=True) 225 buildStores("strh", size=2) 226 buildStores("strht", size=2, user=True) 227 228 buildDoubleStores("strd") | 216 def buildStores(mnem, size=4, sign=False, user=False): 217 buildImmStore(mnem, True, True, True, size, sign, user) 218 buildRegStore(mnem, True, True, True, size, sign, user) 219 buildImmStore(mnem, True, False, True, size, sign, user) 220 buildRegStore(mnem, True, False, True, size, sign, user) 221 buildImmStore(mnem, False, True, True, size, sign, user) 222 buildRegStore(mnem, False, True, True, size, sign, user) 223 buildImmStore(mnem, False, False, True, size, sign, user) --- 20 unchanged lines hidden (view full) --- 244 buildStores("str") 245 buildStores("strt", user=True) 246 buildStores("strb", size=1) 247 buildStores("strbt", size=1, user=True) 248 buildStores("strh", size=2) 249 buildStores("strht", size=2, user=True) 250 251 buildDoubleStores("strd") |
252 253 buildImmStore("strex", False, True, False, size=4, strex=True) 254 buildImmStore("strexh", False, True, False, size=2, strex=True) 255 buildImmStore("strexb", False, True, False, size=1, strex=True) 256 buildDoubleImmStore("strexd", False, True, False, strex=True) |
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229}}; | 257}}; |