str.isa (7294:fda2c00880db) | str.isa (7296:27c60324ec4d) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 79 unchanged lines hidden (view full) --- 88 op = " -" 89 90 offset = op + " imm" 91 eaCode = "EA = Base" 92 if not post: 93 eaCode += offset 94 eaCode += ";" 95 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 79 unchanged lines hidden (view full) --- 88 op = " -" 89 90 offset = op + " imm" 91 eaCode = "EA = Base" 92 if not post: 93 eaCode += offset 94 eaCode += ";" 95 |
96 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) | 96 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 97 { "suffix" : buildMemSuffix(sign, size) } |
97 if writeback: 98 accCode += "Base = Base %s;\n" % offset 99 base = buildMemBase("MemoryImm", post, writeback) 100 101 emitStore(name, Name, True, eaCode, accCode, \ 102 ["ArmISA::TLB::MustBeOne", \ 103 "ArmISA::TLB::AllowUnaligned", \ 104 "%d" % (size - 1)], [], base) --- 11 unchanged lines hidden (view full) --- 116 117 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 118 " shiftType, CondCodes<29:>)" 119 eaCode = "EA = Base" 120 if not post: 121 eaCode += offset 122 eaCode += ";" 123 | 98 if writeback: 99 accCode += "Base = Base %s;\n" % offset 100 base = buildMemBase("MemoryImm", post, writeback) 101 102 emitStore(name, Name, True, eaCode, accCode, \ 103 ["ArmISA::TLB::MustBeOne", \ 104 "ArmISA::TLB::AllowUnaligned", \ 105 "%d" % (size - 1)], [], base) --- 11 unchanged lines hidden (view full) --- 117 118 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 119 " shiftType, CondCodes<29:>)" 120 eaCode = "EA = Base" 121 if not post: 122 eaCode += offset 123 eaCode += ";" 124 |
124 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) | 125 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 126 { "suffix" : buildMemSuffix(sign, size) } |
125 if writeback: 126 accCode += "Base = Base %s;\n" % offset 127 base = buildMemBase("MemoryReg", post, writeback) 128 129 emitStore(name, Name, False, eaCode, accCode, \ 130 ["ArmISA::TLB::MustBeOne", \ 131 "ArmISA::TLB::AllowUnaligned", \ 132 "%d" % (size - 1)], [], base) --- 8 unchanged lines hidden (view full) --- 141 op = " -" 142 143 offset = op + " imm" 144 eaCode = "EA = Base" 145 if not post: 146 eaCode += offset 147 eaCode += ";" 148 | 127 if writeback: 128 accCode += "Base = Base %s;\n" % offset 129 base = buildMemBase("MemoryReg", post, writeback) 130 131 emitStore(name, Name, False, eaCode, accCode, \ 132 ["ArmISA::TLB::MustBeOne", \ 133 "ArmISA::TLB::AllowUnaligned", \ 134 "%d" % (size - 1)], [], base) --- 8 unchanged lines hidden (view full) --- 143 op = " -" 144 145 offset = op + " imm" 146 eaCode = "EA = Base" 147 if not post: 148 eaCode += offset 149 eaCode += ";" 150 |
149 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' | 151 accCode = ''' 152 CPSR cpsr = Cpsr; 153 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 154 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 155 ''' |
150 if writeback: 151 accCode += "Base = Base %s;\n" % offset 152 base = buildMemBase("MemoryDImm", post, writeback) 153 154 emitStore(name, Name, True, eaCode, accCode, \ 155 ["ArmISA::TLB::MustBeOne", 156 "ArmISA::TLB::AlignWord"], [], base, double=True) 157 --- 8 unchanged lines hidden (view full) --- 166 167 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 168 " shiftType, CondCodes<29:>)" 169 eaCode = "EA = Base" 170 if not post: 171 eaCode += offset 172 eaCode += ";" 173 | 156 if writeback: 157 accCode += "Base = Base %s;\n" % offset 158 base = buildMemBase("MemoryDImm", post, writeback) 159 160 emitStore(name, Name, True, eaCode, accCode, \ 161 ["ArmISA::TLB::MustBeOne", 162 "ArmISA::TLB::AlignWord"], [], base, double=True) 163 --- 8 unchanged lines hidden (view full) --- 172 173 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 174 " shiftType, CondCodes<29:>)" 175 eaCode = "EA = Base" 176 if not post: 177 eaCode += offset 178 eaCode += ";" 179 |
174 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' | 180 accCode = ''' 181 CPSR cpsr = Cpsr; 182 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 183 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 184 ''' |
175 if writeback: 176 accCode += "Base = Base %s;\n" % offset 177 base = buildMemBase("MemoryDReg", post, writeback) 178 179 emitStore(name, Name, False, eaCode, accCode, \ 180 ["ArmISA::TLB::MustBeOne", \ 181 "ArmISA::TLB::AlignWord"], [], base, double=True) 182 --- 37 unchanged lines hidden --- | 185 if writeback: 186 accCode += "Base = Base %s;\n" % offset 187 base = buildMemBase("MemoryDReg", post, writeback) 188 189 emitStore(name, Name, False, eaCode, accCode, \ 190 ["ArmISA::TLB::MustBeOne", \ 191 "ArmISA::TLB::AlignWord"], [], base, double=True) 192 --- 37 unchanged lines hidden --- |