str.isa (7279:157b02cc0ba1) | str.isa (7294:fda2c00880db) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 84 unchanged lines hidden (view full) --- 93 eaCode += offset 94 eaCode += ";" 95 96 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 97 if writeback: 98 accCode += "Base = Base %s;\n" % offset 99 base = buildMemBase("MemoryImm", post, writeback) 100 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 84 unchanged lines hidden (view full) --- 93 eaCode += offset 94 eaCode += ";" 95 96 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 97 if writeback: 98 accCode += "Base = Base %s;\n" % offset 99 base = buildMemBase("MemoryImm", post, writeback) 100 |
101 emitStore(name, Name, True, eaCode, accCode, [], [], base) | 101 emitStore(name, Name, True, eaCode, accCode, \ 102 ["ArmISA::TLB::MustBeOne", \ 103 "ArmISA::TLB::AllowUnaligned", \ 104 "%d" % (size - 1)], [], base) |
102 103 def buildRegStore(mnem, post, add, writeback, \ 104 size=4, sign=False, user=False): 105 name = mnem 106 Name = storeRegClassName(post, add, writeback, 107 size, sign, user) 108 109 if add: --- 8 unchanged lines hidden (view full) --- 118 eaCode += offset 119 eaCode += ";" 120 121 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 122 if writeback: 123 accCode += "Base = Base %s;\n" % offset 124 base = buildMemBase("MemoryReg", post, writeback) 125 | 105 106 def buildRegStore(mnem, post, add, writeback, \ 107 size=4, sign=False, user=False): 108 name = mnem 109 Name = storeRegClassName(post, add, writeback, 110 size, sign, user) 111 112 if add: --- 8 unchanged lines hidden (view full) --- 121 eaCode += offset 122 eaCode += ";" 123 124 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 125 if writeback: 126 accCode += "Base = Base %s;\n" % offset 127 base = buildMemBase("MemoryReg", post, writeback) 128 |
126 emitStore(name, Name, False, eaCode, accCode, [], [], base) | 129 emitStore(name, Name, False, eaCode, accCode, \ 130 ["ArmISA::TLB::MustBeOne", \ 131 "ArmISA::TLB::AllowUnaligned", \ 132 "%d" % (size - 1)], [], base) |
127 128 def buildDoubleImmStore(mnem, post, add, writeback): 129 name = mnem 130 Name = storeDoubleImmClassName(post, add, writeback) 131 132 if add: 133 op = " +" 134 else: --- 6 unchanged lines hidden (view full) --- 141 eaCode += ";" 142 143 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' 144 if writeback: 145 accCode += "Base = Base %s;\n" % offset 146 base = buildMemBase("MemoryDImm", post, writeback) 147 148 emitStore(name, Name, True, eaCode, accCode, \ | 133 134 def buildDoubleImmStore(mnem, post, add, writeback): 135 name = mnem 136 Name = storeDoubleImmClassName(post, add, writeback) 137 138 if add: 139 op = " +" 140 else: --- 6 unchanged lines hidden (view full) --- 147 eaCode += ";" 148 149 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' 150 if writeback: 151 accCode += "Base = Base %s;\n" % offset 152 base = buildMemBase("MemoryDImm", post, writeback) 153 154 emitStore(name, Name, True, eaCode, accCode, \ |
149 [], [], base, double=True) | 155 ["ArmISA::TLB::MustBeOne", 156 "ArmISA::TLB::AlignWord"], [], base, double=True) |
150 151 def buildDoubleRegStore(mnem, post, add, writeback): 152 name = mnem 153 Name = storeDoubleRegClassName(post, add, writeback) 154 155 if add: 156 op = " +" 157 else: --- 7 unchanged lines hidden (view full) --- 165 eaCode += ";" 166 167 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' 168 if writeback: 169 accCode += "Base = Base %s;\n" % offset 170 base = buildMemBase("MemoryDReg", post, writeback) 171 172 emitStore(name, Name, False, eaCode, accCode, \ | 157 158 def buildDoubleRegStore(mnem, post, add, writeback): 159 name = mnem 160 Name = storeDoubleRegClassName(post, add, writeback) 161 162 if add: 163 op = " +" 164 else: --- 7 unchanged lines hidden (view full) --- 172 eaCode += ";" 173 174 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' 175 if writeback: 176 accCode += "Base = Base %s;\n" % offset 177 base = buildMemBase("MemoryDReg", post, writeback) 178 179 emitStore(name, Name, False, eaCode, accCode, \ |
173 [], [], base, double=True) | 180 ["ArmISA::TLB::MustBeOne", \ 181 "ArmISA::TLB::AlignWord"], [], base, double=True) |
174 175 def buildStores(mnem, size=4, sign=False, user=False): 176 buildImmStore(mnem, True, True, True, size, sign, user) 177 buildRegStore(mnem, True, True, True, size, sign, user) 178 buildImmStore(mnem, True, False, True, size, sign, user) 179 buildRegStore(mnem, True, False, True, size, sign, user) 180 buildImmStore(mnem, False, True, True, size, sign, user) 181 buildRegStore(mnem, False, True, True, size, sign, user) --- 30 unchanged lines hidden --- | 182 183 def buildStores(mnem, size=4, sign=False, user=False): 184 buildImmStore(mnem, True, True, True, size, sign, user) 185 buildRegStore(mnem, True, True, True, size, sign, user) 186 buildImmStore(mnem, True, False, True, size, sign, user) 187 buildRegStore(mnem, True, False, True, size, sign, user) 188 buildImmStore(mnem, False, True, True, size, sign, user) 189 buildRegStore(mnem, False, True, True, size, sign, user) --- 30 unchanged lines hidden --- |