str.isa (7132:83b433d6e600) | str.isa (7279:157b02cc0ba1) |
---|---|
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 47 unchanged lines hidden (view full) --- 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 47 unchanged lines hidden (view full) --- 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 |
64 def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base): | 64 def emitStore(name, Name, imm, eaCode, accCode, \ 65 memFlags, instFlags, base, double=False): |
65 global header_output, decoder_output, exec_output 66 67 (newHeader, 68 newDecoder, 69 newExec) = loadStoreBase(name, Name, imm, 70 eaCode, accCode, | 66 global header_output, decoder_output, exec_output 67 68 (newHeader, 69 newDecoder, 70 newExec) = loadStoreBase(name, Name, imm, 71 eaCode, accCode, |
71 memFlags, instFlags, | 72 memFlags, instFlags, double, |
72 base, execTemplateBase = 'Store') 73 74 header_output += newHeader 75 decoder_output += newDecoder 76 exec_output += newExec 77 78 def buildImmStore(mnem, post, add, writeback, \ 79 size=4, sign=False, user=False): --- 54 unchanged lines hidden (view full) --- 134 op = " -" 135 136 offset = op + " imm" 137 eaCode = "EA = Base" 138 if not post: 139 eaCode += offset 140 eaCode += ";" 141 | 73 base, execTemplateBase = 'Store') 74 75 header_output += newHeader 76 decoder_output += newDecoder 77 exec_output += newExec 78 79 def buildImmStore(mnem, post, add, writeback, \ 80 size=4, sign=False, user=False): --- 54 unchanged lines hidden (view full) --- 135 op = " -" 136 137 offset = op + " imm" 138 eaCode = "EA = Base" 139 if not post: 140 eaCode += offset 141 eaCode += ";" 142 |
142 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' | 143 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' |
143 if writeback: 144 accCode += "Base = Base %s;\n" % offset | 144 if writeback: 145 accCode += "Base = Base %s;\n" % offset |
145 base = buildMemBase("MemoryImm", post, writeback) | 146 base = buildMemBase("MemoryDImm", post, writeback) |
146 | 147 |
147 emitStore(name, Name, True, eaCode, accCode, [], [], base) | 148 emitStore(name, Name, True, eaCode, accCode, \ 149 [], [], base, double=True) |
148 149 def buildDoubleRegStore(mnem, post, add, writeback): 150 name = mnem 151 Name = storeDoubleRegClassName(post, add, writeback) 152 153 if add: 154 op = " +" 155 else: 156 op = " -" 157 158 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 159 " shiftType, CondCodes<29:>)" 160 eaCode = "EA = Base" 161 if not post: 162 eaCode += offset 163 eaCode += ";" 164 | 150 151 def buildDoubleRegStore(mnem, post, add, writeback): 152 name = mnem 153 Name = storeDoubleRegClassName(post, add, writeback) 154 155 if add: 156 op = " +" 157 else: 158 op = " -" 159 160 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 161 " shiftType, CondCodes<29:>)" 162 eaCode = "EA = Base" 163 if not post: 164 eaCode += offset 165 eaCode += ";" 166 |
165 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' | 167 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' |
166 if writeback: 167 accCode += "Base = Base %s;\n" % offset | 168 if writeback: 169 accCode += "Base = Base %s;\n" % offset |
168 base = buildMemBase("MemoryReg", post, writeback) | 170 base = buildMemBase("MemoryDReg", post, writeback) |
169 | 171 |
170 emitStore(name, Name, False, eaCode, accCode, [], [], base) | 172 emitStore(name, Name, False, eaCode, accCode, \ 173 [], [], base, double=True) |
171 172 def buildStores(mnem, size=4, sign=False, user=False): 173 buildImmStore(mnem, True, True, True, size, sign, user) 174 buildRegStore(mnem, True, True, True, size, sign, user) 175 buildImmStore(mnem, True, False, True, size, sign, user) 176 buildRegStore(mnem, True, False, True, size, sign, user) 177 buildImmStore(mnem, False, True, True, size, sign, user) 178 buildRegStore(mnem, False, True, True, size, sign, user) --- 30 unchanged lines hidden --- | 174 175 def buildStores(mnem, size=4, sign=False, user=False): 176 buildImmStore(mnem, True, True, True, size, sign, user) 177 buildRegStore(mnem, True, True, True, size, sign, user) 178 buildImmStore(mnem, True, False, True, size, sign, user) 179 buildRegStore(mnem, True, False, True, size, sign, user) 180 buildImmStore(mnem, False, True, True, size, sign, user) 181 buildRegStore(mnem, False, True, True, size, sign, user) --- 30 unchanged lines hidden --- |