1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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62 if self.add:
63 self.op = " +"
64 else:
65 self.op = " -"
66
67 self.memFlags = ["ArmISA::TLB::MustBeOne"]
68 self.codeBlobs = { "postacc_code" : "" }
69
70 def emitHelper(self, base = 'Memory'):
71
72 global header_output, decoder_output, exec_output
73
74 codeBlobs = self.codeBlobs
75 codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76 (newHeader,
77 newDecoder,
78 newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
79 self.memFlags, [], base)
80
81 header_output += newHeader
82 decoder_output += newDecoder
83 exec_output += newExec
84
85 class SrsInst(LoadStoreInst):
86 execBase = 'Store'
87 decConstBase = 'Srs'

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132 decoder_output += newDecoder
133 exec_output += newExec
134
135 class StoreImmInst(StoreInst):
136 def __init__(self, *args, **kargs):
137 super(StoreImmInst, self).__init__(*args, **kargs)
138 self.offset = self.op + " imm"
139
140 class StoreRegInst(StoreInst):
141 def __init__(self, *args, **kargs):
142 super(StoreRegInst, self).__init__(*args, **kargs)
143 self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
144 " shiftType, CondCodes<29:>)"
145
146 class StoreSingle(StoreInst):
147 def __init__(self, *args, **kargs):
148 super(StoreSingle, self).__init__(*args, **kargs)
149
150 # Build the default class name
151 self.Name = self.nameFunc(self.post, self.add, self.writeback,
152 self.size, self.sign, self.user)

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181 if self.flavor == "fp":
182 accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
183 else:
184 accCode = \
185 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
186 accCode = accCode % \
187 { "suffix" : buildMemSuffix(self.sign, self.size) }
188
189 if self.writeback:
190 accCode += "Base = Base %s;\n" % self.offset
191
192 self.codeBlobs["memacc_code"] = accCode
193
194 # Push it out to the output files
195 base = buildMemBase(self.basePrefix, self.post, self.writeback)
196 self.emitHelper(base)
197
198 def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
199 return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
200
201 class StoreImmEx(StoreImmInst, StoreSingle):
202 execBase = 'StoreEx'
203 decConstBase = 'StoreExImm'
204 basePrefix = 'MemoryExImm'

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212 decConstBase = 'LoadStoreImm'
213 basePrefix = 'MemoryImm'
214 nameFunc = staticmethod(storeImmClassName)
215
216 def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
217 return memClassName("STORE_REG", post, add, writeback, size, sign, user)
218
219 class StoreReg(StoreRegInst, StoreSingle):
220 decConstBase = 'LoadStoreReg'
221 basePrefix = 'MemoryReg'
222 nameFunc = staticmethod(storeRegClassName)
223
224 class StoreDouble(StoreInst):
225 def __init__(self, *args, **kargs):
226 super(StoreDouble, self).__init__(*args, **kargs)
227
228 # Build the default class name

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260 '''
261 else:
262 accCode = '''
263 CPSR cpsr = Cpsr;
264 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
265 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
266 '''
267
268 if self.writeback:
269 accCode += "Base = Base %s;\n" % self.offset
270
271 self.codeBlobs["memacc_code"] = accCode
272
273 # Push it out to the output files
274 base = buildMemBase(self.basePrefix, self.post, self.writeback)
275 self.emitHelper(base)
276
277 def storeDoubleImmClassName(post, add, writeback):
278 return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
279
280 class StoreDoubleImmEx(StoreImmInst, StoreDouble):
281 execBase = 'StoreEx'
282 decConstBase = 'StoreExDImm'
283 basePrefix = 'MemoryExDImm'

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291 decConstBase = 'LoadStoreDImm'
292 basePrefix = 'MemoryDImm'
293 nameFunc = staticmethod(storeDoubleImmClassName)
294
295 def storeDoubleRegClassName(post, add, writeback):
296 return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
297
298 class StoreDoubleReg(StoreRegInst, StoreDouble):
299 decConstBase = 'LoadStoreDReg'
300 basePrefix = 'MemoryDReg'
301 nameFunc = staticmethod(storeDoubleRegClassName)
302
303 def buildStores(mnem, size=4, sign=False, user=False):
304 StoreImm(mnem, True, True, True, size, sign, user).emit()
305 StoreReg(mnem, True, True, True, size, sign, user).emit()
306 StoreImm(mnem, True, False, True, size, sign, user).emit()
307 StoreReg(mnem, True, False, True, size, sign, user).emit()

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