1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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73 memFlags, instFlags, double, strex,
74 base, execTemplateBase = execTemplateBase)
75
76 header_output += newHeader
77 decoder_output += newDecoder
78 exec_output += newExec
79
80 def buildImmStore(mnem, post, add, writeback, \
81 size=4, sign=False, user=False, strex=False):
82 name = mnem
83 Name = storeImmClassName(post, add, writeback, \
84 size, sign, user)
85
86 if add:
87 op = " +"
88 else:
89 op = " -"
90
91 offset = op + " imm"
92 eaCode = "EA = Base"
93 if not post:
94 eaCode += offset
95 eaCode += ";"
96
97 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
98 { "suffix" : buildMemSuffix(sign, size) }
99 if writeback:
100 accCode += "Base = Base %s;\n" % offset
101
102 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
103 if strex:
104 memFlags.append("Request::LLSC")
105 Name = "%s_%s" % (mnem.upper(), Name)
106 base = buildMemBase("MemoryExImm", post, writeback)
107 postAccCode = "Result = !writeResult;"
108 execTemplateBase = 'StoreEx'
109 else:
110 memFlags.append("ArmISA::TLB::AllowUnaligned")
111 base = buildMemBase("MemoryImm", post, writeback)
112 postAccCode = ""
113 execTemplateBase = 'Store'
114
115 emitStore(name, Name, True, eaCode, accCode, postAccCode, \
116 memFlags, [], base, strex=strex,
117 execTemplateBase = execTemplateBase)
118

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174 accCode += "Base = Base %s;\n" % offset
175 base = buildMemBase("MemoryReg", post, writeback)
176
177 emitStore(name, Name, False, eaCode, accCode, "",\
178 ["ArmISA::TLB::MustBeOne", \
179 "ArmISA::TLB::AllowUnaligned", \
180 "%d" % (size - 1)], [], base)
181
182 def buildDoubleImmStore(mnem, post, add, writeback, strex=False):
183 name = mnem
184 Name = storeDoubleImmClassName(post, add, writeback)
185
186 if add:
187 op = " +"
188 else:
189 op = " -"
190
191 offset = op + " imm"
192 eaCode = "EA = Base"
193 if not post:
194 eaCode += offset
195 eaCode += ";"
196
197 accCode = '''
198 CPSR cpsr = Cpsr;
199 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
200 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
201 '''
202 if writeback:
203 accCode += "Base = Base %s;\n" % offset
204
205 memFlags = ["ArmISA::TLB::MustBeOne",
206 "ArmISA::TLB::AlignWord"]
207 if strex:
208 memFlags.append("Request::LLSC")
209 Name = "%s_%s" % (mnem.upper(), Name)
210 base = buildMemBase("MemoryExDImm", post, writeback)
211 postAccCode = "Result = !writeResult;"
212 else:
213 base = buildMemBase("MemoryDImm", post, writeback)
214 postAccCode = ""
215
216 emitStore(name, Name, True, eaCode, accCode, postAccCode, \
217 memFlags, [], base, double=True, strex=strex)
218
219 def buildDoubleRegStore(mnem, post, add, writeback):
220 name = mnem
221 Name = storeDoubleRegClassName(post, add, writeback)
222

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295 buildSrsStores("srs")
296
297 buildDoubleStores("strd")
298
299 buildImmStore("strex", False, True, False, size=4, strex=True)
300 buildImmStore("strexh", False, True, False, size=2, strex=True)
301 buildImmStore("strexb", False, True, False, size=1, strex=True)
302 buildDoubleImmStore("strexd", False, True, False, strex=True)
303}};