macromem.isa (8607:5fb918115c07) macromem.isa (10037:5cac77888310)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR old_cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92
93 CPSR new_cpsr =
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR old_cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92
93 CPSR new_cpsr =
94 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
94 cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, true,
95 sctlr.nmfi, xc->tcBase());
95 Cpsr = ~CondCodesMask & new_cpsr;
96 CondCodesNZ = new_cpsr.nz;
97 CondCodesC = new_cpsr.c;
98 CondCodesV = new_cpsr.v;
99 CondCodesGE = new_cpsr.ge;
100 IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
101 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
102 | (((CPSR)Spsr).it1 & 0x3);

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153 EA = URb + (up ? imm : -imm) -
154 (((CPSR)Cpsr).e ? 4 : 0);
155 ''',
156 'predicate_test': predicateTest},
157 ['IsMicroop'])
158
159 header_output = decoder_output = exec_output = ''
160
96 Cpsr = ~CondCodesMask & new_cpsr;
97 CondCodesNZ = new_cpsr.nz;
98 CondCodesC = new_cpsr.c;
99 CondCodesV = new_cpsr.v;
100 CondCodesGE = new_cpsr.ge;
101 IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
102 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
103 | (((CPSR)Spsr).it1 & 0x3);

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154 EA = URb + (up ? imm : -imm) -
155 (((CPSR)Cpsr).e ? 4 : 0);
156 ''',
157 'predicate_test': predicateTest},
158 ['IsMicroop'])
159
160 header_output = decoder_output = exec_output = ''
161
161 loadIops = (microLdrUopIop, microLdrRetUopIop,
162 microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop)
162 loadIops = (microLdrUopIop, microLdrRetUopIop, microLdrFpUopIop,
163 microLdrDBFpUopIop, microLdrDTFpUopIop)
163 storeIops = (microStrUopIop, microStrFpUopIop,
164 microStrDBFpUopIop, microStrDTFpUopIop)
165 for iop in loadIops + storeIops:
166 header_output += MicroMemDeclare.subst(iop)
167 decoder_output += MicroMemConstructor.subst(iop)
168 for iop in loadIops:
169 exec_output += LoadExecute.subst(iop) + \
170 LoadInitiateAcc.subst(iop) + \
171 LoadCompleteAcc.subst(iop)
172 for iop in storeIops:
173 exec_output += StoreExecute.subst(iop) + \
174 StoreInitiateAcc.subst(iop) + \
175 StoreCompleteAcc.subst(iop)
176}};
177
178let {{
179 exec_output = header_output = ''
180
164 storeIops = (microStrUopIop, microStrFpUopIop,
165 microStrDBFpUopIop, microStrDTFpUopIop)
166 for iop in loadIops + storeIops:
167 header_output += MicroMemDeclare.subst(iop)
168 decoder_output += MicroMemConstructor.subst(iop)
169 for iop in loadIops:
170 exec_output += LoadExecute.subst(iop) + \
171 LoadInitiateAcc.subst(iop) + \
172 LoadCompleteAcc.subst(iop)
173 for iop in storeIops:
174 exec_output += StoreExecute.subst(iop) + \
175 StoreInitiateAcc.subst(iop) + \
176 StoreCompleteAcc.subst(iop)
177}};
178
179let {{
180 exec_output = header_output = ''
181
181 eaCode = 'EA = URa + imm;'
182 eaCode = 'EA = XURa + imm;'
182
183 for size in (1, 2, 3, 4, 6, 8, 12, 16):
184 # Set up the memory access.
185 regs = (size + 3) // 4
186 subst = { "size" : size, "regs" : regs }
187 memDecl = '''
188 union MemUnion {
189 uint8_t bytes[%(size)d];

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587 {'code': 'URa = URb + imm;',
588 'predicate_test': predicateTest},
589 ['IsMicroop'])
590
591 microAddUopCode = '''
592 URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
593 '''
594
183
184 for size in (1, 2, 3, 4, 6, 8, 12, 16):
185 # Set up the memory access.
186 regs = (size + 3) // 4
187 subst = { "size" : size, "regs" : regs }
188 memDecl = '''
189 union MemUnion {
190 uint8_t bytes[%(size)d];

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588 {'code': 'URa = URb + imm;',
589 'predicate_test': predicateTest},
590 ['IsMicroop'])
591
592 microAddUopCode = '''
593 URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
594 '''
595
596 microAddXiUopIop = InstObjParams('addxi_uop', 'MicroAddXiUop',
597 'MicroIntImmXOp',
598 'XURa = XURb + imm;',
599 ['IsMicroop'])
600
601 microAddXiSpAlignUopIop = InstObjParams('addxi_uop', 'MicroAddXiSpAlignUop',
602 'MicroIntImmXOp', '''
603 if (isSP((IntRegIndex) urb) && bits(XURb, 3, 0) &&
604 SPAlignmentCheckEnabled(xc->tcBase())) {
605 return new SPAlignmentFault();
606 }
607 XURa = XURb + imm;
608 ''', ['IsMicroop'])
609
610 microAddXERegUopIop = InstObjParams('addxr_uop', 'MicroAddXERegUop',
611 'MicroIntRegXOp',
612 'XURa = XURb + ' + \
613 'extendReg64(XURc, type, shiftAmt, 64);',
614 ['IsMicroop'])
615
595 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
596 'MicroIntRegOp',
597 {'code': microAddUopCode,
598 'predicate_test': pickPredicate(microAddUopCode)},
599 ['IsMicroop'])
600
601 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
602 'MicroIntImmOp',
603 {'code': 'URa = URb - imm;',
604 'predicate_test': predicateTest},
605 ['IsMicroop'])
606
616 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
617 'MicroIntRegOp',
618 {'code': microAddUopCode,
619 'predicate_test': pickPredicate(microAddUopCode)},
620 ['IsMicroop'])
621
622 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
623 'MicroIntImmOp',
624 {'code': 'URa = URb - imm;',
625 'predicate_test': predicateTest},
626 ['IsMicroop'])
627
628 microSubXiUopIop = InstObjParams('subxi_uop', 'MicroSubXiUop',
629 'MicroIntImmXOp',
630 'XURa = XURb - imm;',
631 ['IsMicroop'])
632
607 microSubUopCode = '''
608 URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
609 '''
610 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
611 'MicroIntRegOp',
612 {'code': microSubUopCode,
613 'predicate_test': pickPredicate(microSubUopCode)},
614 ['IsMicroop'])

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626 ['IsMicroop', 'IsNonSpeculative',
627 'IsSerializeAfter'])
628
629 setPCCPSRDecl = '''
630 CPSR cpsrOrCondCodes = URc;
631 SCTLR sctlr = Sctlr;
632 pNPC = URa;
633 CPSR new_cpsr =
633 microSubUopCode = '''
634 URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
635 '''
636 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
637 'MicroIntRegOp',
638 {'code': microSubUopCode,
639 'predicate_test': pickPredicate(microSubUopCode)},
640 ['IsMicroop'])

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652 ['IsMicroop', 'IsNonSpeculative',
653 'IsSerializeAfter'])
654
655 setPCCPSRDecl = '''
656 CPSR cpsrOrCondCodes = URc;
657 SCTLR sctlr = Sctlr;
658 pNPC = URa;
659 CPSR new_cpsr =
634 cpsrWriteByInstr(cpsrOrCondCodes, URb,
635 0xF, true, sctlr.nmfi);
660 cpsrWriteByInstr(cpsrOrCondCodes, URb, Scr, Nsacr,
661 0xF, true, sctlr.nmfi, xc->tcBase());
636 Cpsr = ~CondCodesMask & new_cpsr;
637 NextThumb = new_cpsr.t;
638 NextJazelle = new_cpsr.j;
639 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
640 | (((CPSR)URb).it1 & 0x3);
641 CondCodesNZ = new_cpsr.nz;
642 CondCodesC = new_cpsr.c;
643 CondCodesV = new_cpsr.v;
644 CondCodesGE = new_cpsr.ge;
645 '''
646
647 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
648 'MicroSetPCCPSR',
649 {'code': setPCCPSRDecl,
650 'predicate_test': predicateTest},
651 ['IsMicroop'])
652
653 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
662 Cpsr = ~CondCodesMask & new_cpsr;
663 NextThumb = new_cpsr.t;
664 NextJazelle = new_cpsr.j;
665 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
666 | (((CPSR)URb).it1 & 0x3);
667 CondCodesNZ = new_cpsr.nz;
668 CondCodesC = new_cpsr.c;
669 CondCodesV = new_cpsr.v;
670 CondCodesGE = new_cpsr.ge;
671 '''
672
673 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
674 'MicroSetPCCPSR',
675 {'code': setPCCPSRDecl,
676 'predicate_test': predicateTest},
677 ['IsMicroop'])
678
679 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
680 MicroIntImmDeclare.subst(microAddXiUopIop) + \
681 MicroIntImmDeclare.subst(microAddXiSpAlignUopIop) + \
654 MicroIntImmDeclare.subst(microSubiUopIop) + \
682 MicroIntImmDeclare.subst(microSubiUopIop) + \
683 MicroIntImmDeclare.subst(microSubXiUopIop) + \
655 MicroIntRegDeclare.subst(microAddUopIop) + \
656 MicroIntRegDeclare.subst(microSubUopIop) + \
684 MicroIntRegDeclare.subst(microAddUopIop) + \
685 MicroIntRegDeclare.subst(microSubUopIop) + \
686 MicroIntXERegDeclare.subst(microAddXERegUopIop) + \
657 MicroIntMovDeclare.subst(microUopRegMovIop) + \
658 MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
659 MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
660
661 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
687 MicroIntMovDeclare.subst(microUopRegMovIop) + \
688 MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
689 MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
690
691 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
692 MicroIntImmXConstructor.subst(microAddXiUopIop) + \
693 MicroIntImmXConstructor.subst(microAddXiSpAlignUopIop) + \
662 MicroIntImmConstructor.subst(microSubiUopIop) + \
694 MicroIntImmConstructor.subst(microSubiUopIop) + \
695 MicroIntImmXConstructor.subst(microSubXiUopIop) + \
663 MicroIntRegConstructor.subst(microAddUopIop) + \
664 MicroIntRegConstructor.subst(microSubUopIop) + \
696 MicroIntRegConstructor.subst(microAddUopIop) + \
697 MicroIntRegConstructor.subst(microSubUopIop) + \
698 MicroIntXERegConstructor.subst(microAddXERegUopIop) + \
665 MicroIntMovConstructor.subst(microUopRegMovIop) + \
666 MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
667 MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
668
669 exec_output = PredOpExecute.subst(microAddiUopIop) + \
699 MicroIntMovConstructor.subst(microUopRegMovIop) + \
700 MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
701 MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
702
703 exec_output = PredOpExecute.subst(microAddiUopIop) + \
704 BasicExecute.subst(microAddXiUopIop) + \
705 BasicExecute.subst(microAddXiSpAlignUopIop) + \
670 PredOpExecute.subst(microSubiUopIop) + \
706 PredOpExecute.subst(microSubiUopIop) + \
707 BasicExecute.subst(microSubXiUopIop) + \
671 PredOpExecute.subst(microAddUopIop) + \
672 PredOpExecute.subst(microSubUopIop) + \
708 PredOpExecute.subst(microAddUopIop) + \
709 PredOpExecute.subst(microSubUopIop) + \
710 BasicExecute.subst(microAddXERegUopIop) + \
673 PredOpExecute.subst(microUopRegMovIop) + \
674 PredOpExecute.subst(microUopRegMovRetIop) + \
675 PredOpExecute.subst(microUopSetPCCPSRIop)
676
677}};
678
679let {{
680 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
681 header_output = MacroMemDeclare.subst(iop)
682 decoder_output = MacroMemConstructor.subst(iop)
683
711 PredOpExecute.subst(microUopRegMovIop) + \
712 PredOpExecute.subst(microUopRegMovRetIop) + \
713 PredOpExecute.subst(microUopSetPCCPSRIop)
714
715}};
716
717let {{
718 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
719 header_output = MacroMemDeclare.subst(iop)
720 decoder_output = MacroMemConstructor.subst(iop)
721
722 iop = InstObjParams("ldpstp", "LdpStp", 'PairMemOp', "", [])
723 header_output += PairMemDeclare.subst(iop)
724 decoder_output += PairMemConstructor.subst(iop)
725
726 iopImm = InstObjParams("bigfpmemimm", "BigFpMemImm", "BigFpMemImmOp", "")
727 iopPre = InstObjParams("bigfpmempre", "BigFpMemPre", "BigFpMemPreOp", "")
728 iopPost = InstObjParams("bigfpmempost", "BigFpMemPost", "BigFpMemPostOp", "")
729 for iop in (iopImm, iopPre, iopPost):
730 header_output += BigFpMemImmDeclare.subst(iop)
731 decoder_output += BigFpMemImmConstructor.subst(iop)
732
733 iop = InstObjParams("bigfpmemreg", "BigFpMemReg", "BigFpMemRegOp", "")
734 header_output += BigFpMemRegDeclare.subst(iop)
735 decoder_output += BigFpMemRegConstructor.subst(iop)
736
737 iop = InstObjParams("bigfpmemlit", "BigFpMemLit", "BigFpMemLitOp", "")
738 header_output += BigFpMemLitDeclare.subst(iop)
739 decoder_output += BigFpMemLitConstructor.subst(iop)
740
684 iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
685 header_output += VMemMultDeclare.subst(iop)
686 decoder_output += VMemMultConstructor.subst(iop)
687
688 iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
689 header_output += VMemSingleDeclare.subst(iop)
690 decoder_output += VMemSingleConstructor.subst(iop)
691

--- 12 unchanged lines hidden --- 		741 iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
742 header_output += VMemMultDeclare.subst(iop)
743 decoder_output += VMemMultConstructor.subst(iop)
744
745 iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
746 header_output += VMemSingleDeclare.subst(iop)
747 decoder_output += VMemSingleConstructor.subst(iop)
748

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