macromem.isa (8303:5a95f1d2494e) macromem.isa (8304:16911ff780d3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 75 unchanged lines hidden (view full) ---

84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR old_cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 75 unchanged lines hidden (view full) ---

84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR old_cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92 old_cpsr.nz = CondCodesNZ;
93 old_cpsr.c = CondCodesC;
94 old_cpsr.v = CondCodesV;
95 old_cpsr.ge = CondCodesGE;
96
97 CPSR new_cpsr =
98 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
99 Cpsr = ~CondCodesMask & new_cpsr;
100 CondCodesNZ = new_cpsr.nz;
101 CondCodesC = new_cpsr.c;
102 CondCodesV = new_cpsr.v;
103 CondCodesGE = new_cpsr.ge;

--- 479 unchanged lines hidden (view full) ---

583
584let {{
585 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
586 'MicroIntImmOp',
587 {'code': 'URa = URb + imm;',
588 'predicate_test': predicateTest},
589 ['IsMicroop'])
590
92
93 CPSR new_cpsr =
94 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
95 Cpsr = ~CondCodesMask & new_cpsr;
96 CondCodesNZ = new_cpsr.nz;
97 CondCodesC = new_cpsr.c;
98 CondCodesV = new_cpsr.v;
99 CondCodesGE = new_cpsr.ge;

--- 479 unchanged lines hidden (view full) ---

579
580let {{
581 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
582 'MicroIntImmOp',
583 {'code': 'URa = URb + imm;',
584 'predicate_test': predicateTest},
585 ['IsMicroop'])
586
587 microAddUopCode = '''
588 URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
589 '''
590
591 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
592 'MicroIntRegOp',
591 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
592 'MicroIntRegOp',
593 {'code':
594 '''URa = URb + shift_rm_imm(URc, shiftAmt,
595 shiftType,
596 CondCodesC);
597 ''',
598 'predicate_test': predicateTest},
593 {'code': microAddUopCode,
594 'predicate_test': pickPredicate(microAddUopCode)},
599 ['IsMicroop'])
600
601 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
602 'MicroIntImmOp',
603 {'code': 'URa = URb - imm;',
604 'predicate_test': predicateTest},
605 ['IsMicroop'])
606
595 ['IsMicroop'])
596
597 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
598 'MicroIntImmOp',
599 {'code': 'URa = URb - imm;',
600 'predicate_test': predicateTest},
601 ['IsMicroop'])
602
603 microSubUopCode = '''
604 URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
605 '''
607 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
608 'MicroIntRegOp',
606 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
607 'MicroIntRegOp',
609 {'code':
610 '''URa = URb - shift_rm_imm(URc, shiftAmt,
611 shiftType,
612 CondCodesC);
613 ''',
614 'predicate_test': predicateTest},
608 {'code': microSubUopCode,
609 'predicate_test': pickPredicate(microSubUopCode)},
615 ['IsMicroop'])
616
617 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
618 'MicroIntMov',
619 {'code': 'IWRa = URb;',
620 'predicate_test': predicateTest},
621 ['IsMicroop'])
622

--- 82 unchanged lines hidden --- 		610 ['IsMicroop'])
611
612 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
613 'MicroIntMov',
614 {'code': 'IWRa = URb;',
615 'predicate_test': predicateTest},
616 ['IsMicroop'])
617

--- 82 unchanged lines hidden ---