macromem.isa (8302:9f23d01421de) macromem.isa (8303:5a95f1d2494e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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82 'ea_code': vfpEnabledCheckCode + '''
83 EA = URb + (up ? imm : -imm) -
84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 73 unchanged lines hidden (view full) ---

82 'ea_code': vfpEnabledCheckCode + '''
83 EA = URb + (up ? imm : -imm) -
84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR cpsr = Cpsr;
90 CPSR old_cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
91 SCTLR sctlr = Sctlr;
92 uint32_t newCpsr =
93 cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE,
94 Spsr, 0xF, true, sctlr.nmfi);
95 Cpsr = ~CondCodesMask & newCpsr;
96 CondCodesF = CondCodesMaskF & newCpsr;
97 CondCodesGE = CondCodesMaskGE & newCpsr;
98 IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
92 old_cpsr.nz = CondCodesNZ;
93 old_cpsr.c = CondCodesC;
94 old_cpsr.v = CondCodesV;
95 old_cpsr.ge = CondCodesGE;
96
97 CPSR new_cpsr =
98 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
99 Cpsr = ~CondCodesMask & new_cpsr;
100 CondCodesNZ = new_cpsr.nz;
101 CondCodesC = new_cpsr.c;
102 CondCodesV = new_cpsr.v;
103 CondCodesGE = new_cpsr.ge;
104 IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
99 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
100 | (((CPSR)Spsr).it1 & 0x3);
101 SevMailbox = 1;
102 '''
103
104 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
105 'MicroMemOp',
106 {'memacc_code':

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582 'predicate_test': predicateTest},
583 ['IsMicroop'])
584
585 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
586 'MicroIntRegOp',
587 {'code':
588 '''URa = URb + shift_rm_imm(URc, shiftAmt,
589 shiftType,
105 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
106 | (((CPSR)Spsr).it1 & 0x3);
107 SevMailbox = 1;
108 '''
109
110 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
111 'MicroMemOp',
112 {'memacc_code':

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588 'predicate_test': predicateTest},
589 ['IsMicroop'])
590
591 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
592 'MicroIntRegOp',
593 {'code':
594 '''URa = URb + shift_rm_imm(URc, shiftAmt,
595 shiftType,
590 CondCodesF<29:>);
596 CondCodesC);
591 ''',
592 'predicate_test': predicateTest},
593 ['IsMicroop'])
594
595 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
596 'MicroIntImmOp',
597 {'code': 'URa = URb - imm;',
598 'predicate_test': predicateTest},
599 ['IsMicroop'])
600
601 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
602 'MicroIntRegOp',
603 {'code':
604 '''URa = URb - shift_rm_imm(URc, shiftAmt,
605 shiftType,
597 ''',
598 'predicate_test': predicateTest},
599 ['IsMicroop'])
600
601 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
602 'MicroIntImmOp',
603 {'code': 'URa = URb - imm;',
604 'predicate_test': predicateTest},
605 ['IsMicroop'])
606
607 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
608 'MicroIntRegOp',
609 {'code':
610 '''URa = URb - shift_rm_imm(URc, shiftAmt,
611 shiftType,
606 CondCodesF<29:>);
612 CondCodesC);
607 ''',
608 'predicate_test': predicateTest},
609 ['IsMicroop'])
610
611 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
612 'MicroIntMov',
613 {'code': 'IWRa = URb;',
614 'predicate_test': predicateTest},

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620 'predicate_test': predicateTest},
621 ['IsMicroop', 'IsNonSpeculative',
622 'IsSerializeAfter'])
623
624 setPCCPSRDecl = '''
625 CPSR cpsrOrCondCodes = URc;
626 SCTLR sctlr = Sctlr;
627 pNPC = URa;
613 ''',
614 'predicate_test': predicateTest},
615 ['IsMicroop'])
616
617 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
618 'MicroIntMov',
619 {'code': 'IWRa = URb;',
620 'predicate_test': predicateTest},

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626 'predicate_test': predicateTest},
627 ['IsMicroop', 'IsNonSpeculative',
628 'IsSerializeAfter'])
629
630 setPCCPSRDecl = '''
631 CPSR cpsrOrCondCodes = URc;
632 SCTLR sctlr = Sctlr;
633 pNPC = URa;
628 uint32_t newCpsr =
634 CPSR new_cpsr =
629 cpsrWriteByInstr(cpsrOrCondCodes, URb,
630 0xF, true, sctlr.nmfi);
635 cpsrWriteByInstr(cpsrOrCondCodes, URb,
636 0xF, true, sctlr.nmfi);
631 Cpsr = ~CondCodesMask & newCpsr;
632 NextThumb = ((CPSR)newCpsr).t;
633 NextJazelle = ((CPSR)newCpsr).j;
637 Cpsr = ~CondCodesMask & new_cpsr;
638 NextThumb = new_cpsr.t;
639 NextJazelle = new_cpsr.j;
634 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
635 | (((CPSR)URb).it1 & 0x3);
640 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
641 | (((CPSR)URb).it1 & 0x3);
636 CondCodesF = CondCodesMaskF & newCpsr;
637 CondCodesGE = CondCodesMaskGE & newCpsr;
642 CondCodesNZ = new_cpsr.nz;
643 CondCodesC = new_cpsr.c;
644 CondCodesV = new_cpsr.v;
645 CondCodesGE = new_cpsr.ge;
638 '''
639
640 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
641 'MicroSetPCCPSR',
642 {'code': setPCCPSRDecl,
643 'predicate_test': predicateTest},
644 ['IsMicroop'])
645

--- 51 unchanged lines hidden --- 		646 '''
647
648 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
649 'MicroSetPCCPSR',
650 {'code': setPCCPSRDecl,
651 'predicate_test': predicateTest},
652 ['IsMicroop'])
653

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