macromem.isa (8285:c38905a6fa32) macromem.isa (8301:858384f3af1c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92 uint32_t newCpsr =
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92 uint32_t newCpsr =
93 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
93 cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE,
94 Spsr, 0xF, true, sctlr.nmfi);
94 Cpsr = ~CondCodesMask & newCpsr;
95 Cpsr = ~CondCodesMask & newCpsr;
95 CondCodes = CondCodesMask & newCpsr;
96 CondCodesF = CondCodesMaskF & newCpsr;
97 CondCodesQ = CondCodesMaskQ & newCpsr;
98 CondCodesGE = CondCodesMaskGE & newCpsr;
96 IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
97 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
98 | (((CPSR)Spsr).it1 & 0x3);
99 SevMailbox = 1;
100 '''
101
102 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
103 'MicroMemOp',

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580 'predicate_test': predicateTest},
581 ['IsMicroop'])
582
583 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
584 'MicroIntRegOp',
585 {'code':
586 '''URa = URb + shift_rm_imm(URc, shiftAmt,
587 shiftType,
99 IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
100 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
101 | (((CPSR)Spsr).it1 & 0x3);
102 SevMailbox = 1;
103 '''
104
105 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
106 'MicroMemOp',

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583 'predicate_test': predicateTest},
584 ['IsMicroop'])
585
586 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
587 'MicroIntRegOp',
588 {'code':
589 '''URa = URb + shift_rm_imm(URc, shiftAmt,
590 shiftType,
588 CondCodes<29:>);
591 CondCodesF<29:>);
589 ''',
590 'predicate_test': predicateTest},
591 ['IsMicroop'])
592
593 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
594 'MicroIntImmOp',
595 {'code': 'URa = URb - imm;',
596 'predicate_test': predicateTest},
597 ['IsMicroop'])
598
599 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
600 'MicroIntRegOp',
601 {'code':
602 '''URa = URb - shift_rm_imm(URc, shiftAmt,
603 shiftType,
592 ''',
593 'predicate_test': predicateTest},
594 ['IsMicroop'])
595
596 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
597 'MicroIntImmOp',
598 {'code': 'URa = URb - imm;',
599 'predicate_test': predicateTest},
600 ['IsMicroop'])
601
602 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
603 'MicroIntRegOp',
604 {'code':
605 '''URa = URb - shift_rm_imm(URc, shiftAmt,
606 shiftType,
604 CondCodes<29:>);
607 CondCodesF<29:>);
605 ''',
606 'predicate_test': predicateTest},
607 ['IsMicroop'])
608
609 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
610 'MicroIntMov',
611 {'code': 'IWRa = URb;',
612 'predicate_test': predicateTest},

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626 uint32_t newCpsr =
627 cpsrWriteByInstr(cpsrOrCondCodes, URb,
628 0xF, true, sctlr.nmfi);
629 Cpsr = ~CondCodesMask & newCpsr;
630 NextThumb = ((CPSR)newCpsr).t;
631 NextJazelle = ((CPSR)newCpsr).j;
632 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
633 | (((CPSR)URb).it1 & 0x3);
608 ''',
609 'predicate_test': predicateTest},
610 ['IsMicroop'])
611
612 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
613 'MicroIntMov',
614 {'code': 'IWRa = URb;',
615 'predicate_test': predicateTest},

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629 uint32_t newCpsr =
630 cpsrWriteByInstr(cpsrOrCondCodes, URb,
631 0xF, true, sctlr.nmfi);
632 Cpsr = ~CondCodesMask & newCpsr;
633 NextThumb = ((CPSR)newCpsr).t;
634 NextJazelle = ((CPSR)newCpsr).j;
635 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
636 | (((CPSR)URb).it1 & 0x3);
634 CondCodes = CondCodesMask & newCpsr;
637 CondCodesF = CondCodesMaskF & newCpsr;
638 CondCodesQ = CondCodesMaskQ & newCpsr;
639 CondCodesGE = CondCodesMaskGE & newCpsr;
635 '''
636
637 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
638 'MicroSetPCCPSR',
639 {'code': setPCCPSRDecl,
640 'predicate_test': predicateTest},
641 ['IsMicroop'])
642

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641
642 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
643 'MicroSetPCCPSR',
644 {'code': setPCCPSRDecl,
645 'predicate_test': predicateTest},
646 ['IsMicroop'])
647

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