| macromem.isa (8148:93982cb5044c) | macromem.isa (8205:7ecbffb674aa) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 80 unchanged lines hidden (view full) --- 89 microRetUopCode = ''' 90 CPSR cpsr = Cpsr; 91 SCTLR sctlr = Sctlr; 92 uint32_t newCpsr = 93 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 94 Cpsr = ~CondCodesMask & newCpsr; 95 CondCodes = CondCodesMask & newCpsr; 96 IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 80 unchanged lines hidden (view full) --- 89 microRetUopCode = ''' 90 CPSR cpsr = Cpsr; 91 SCTLR sctlr = Sctlr; 92 uint32_t newCpsr = 93 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 94 Cpsr = ~CondCodesMask & newCpsr; 95 CondCodes = CondCodesMask & newCpsr; 96 IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); |
| 97 ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) | 97 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) |
| 98 | (((CPSR)Spsr).it1 & 0x3); 99 ''' 100 101 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 102 'MicroMemOp', 103 {'memacc_code': 104 microRetUopCode % 'Mem.uw', 105 'ea_code': --- 517 unchanged lines hidden (view full) --- 623 SCTLR sctlr = Sctlr; 624 pNPC = URa; 625 uint32_t newCpsr = 626 cpsrWriteByInstr(cpsrOrCondCodes, URb, 627 0xF, true, sctlr.nmfi); 628 Cpsr = ~CondCodesMask & newCpsr; 629 NextThumb = ((CPSR)newCpsr).t; 630 NextJazelle = ((CPSR)newCpsr).j; | 98 | (((CPSR)Spsr).it1 & 0x3); 99 ''' 100 101 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 102 'MicroMemOp', 103 {'memacc_code': 104 microRetUopCode % 'Mem.uw', 105 'ea_code': --- 517 unchanged lines hidden (view full) --- 623 SCTLR sctlr = Sctlr; 624 pNPC = URa; 625 uint32_t newCpsr = 626 cpsrWriteByInstr(cpsrOrCondCodes, URb, 627 0xF, true, sctlr.nmfi); 628 Cpsr = ~CondCodesMask & newCpsr; 629 NextThumb = ((CPSR)newCpsr).t; 630 NextJazelle = ((CPSR)newCpsr).j; |
| 631 ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC) | 631 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) |
| 632 | (((CPSR)URb).it1 & 0x3); 633 CondCodes = CondCodesMask & newCpsr; 634 ''' 635 636 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', 637 'MicroSetPCCPSR', 638 {'code': setPCCPSRDecl, 639 'predicate_test': predicateTest}, --- 53 unchanged lines hidden --- | 632 | (((CPSR)URb).it1 & 0x3); 633 CondCodes = CondCodesMask & newCpsr; 634 ''' 635 636 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', 637 'MicroSetPCCPSR', 638 {'code': setPCCPSRDecl, 639 'predicate_test': predicateTest}, --- 53 unchanged lines hidden --- |