macromem.isa (8140:7449084b1612) macromem.isa (8148:93982cb5044c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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81 {'memacc_code': microLdrFpUopCode,
82 'ea_code': vfpEnabledCheckCode + '''
83 EA = URb + (up ? imm : -imm) -
84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 72 unchanged lines hidden (view full) ---

81 {'memacc_code': microLdrFpUopCode,
82 'ea_code': vfpEnabledCheckCode + '''
83 EA = URb + (up ? imm : -imm) -
84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microLdrRetUopCode = '''
89 microRetUopCode = '''
90 CPSR cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92 uint32_t newCpsr =
93 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
94 Cpsr = ~CondCodesMask & newCpsr;
95 CondCodes = CondCodesMask & newCpsr;
90 CPSR cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92 uint32_t newCpsr =
93 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
94 Cpsr = ~CondCodesMask & newCpsr;
95 CondCodes = CondCodesMask & newCpsr;
96 IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
96 IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
97 ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
98 | (((CPSR)Spsr).it1 & 0x3);
99 '''
97 ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
98 | (((CPSR)Spsr).it1 & 0x3);
99 '''
100
100 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
101 'MicroMemOp',
101 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
102 'MicroMemOp',
102 {'memacc_code': microLdrRetUopCode,
103 {'memacc_code':
104 microRetUopCode % 'Mem.uw',
103 'ea_code':
104 'EA = URb + (up ? imm : -imm);',
105 'predicate_test': condPredicateTest},
105 'ea_code':
106 'EA = URb + (up ? imm : -imm);',
107 'predicate_test': condPredicateTest},
106 ['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
108 ['IsMicroop','IsNonSpeculative',
109 'IsSerializeAfter'])
107
108 microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
109 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
110 'MicroMemOp',
111 {'memacc_code': microStrUopCode,
112 'postacc_code': "",
113 'ea_code': 'EA = URb + (up ? imm : -imm);',
114 'predicate_test': predicateTest},

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603 ['IsMicroop'])
604
605 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
606 'MicroIntMov',
607 {'code': 'IWRa = URb;',
608 'predicate_test': predicateTest},
609 ['IsMicroop'])
610
110
111 microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
112 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
113 'MicroMemOp',
114 {'memacc_code': microStrUopCode,
115 'postacc_code': "",
116 'ea_code': 'EA = URb + (up ? imm : -imm);',
117 'predicate_test': predicateTest},

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606 ['IsMicroop'])
607
608 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
609 'MicroIntMov',
610 {'code': 'IWRa = URb;',
611 'predicate_test': predicateTest},
612 ['IsMicroop'])
613
614 microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
615 'MicroIntMov',
616 {'code': microRetUopCode % 'URb',
617 'predicate_test': predicateTest},
618 ['IsMicroop', 'IsNonSpeculative',
619 'IsSerializeAfter'])
620
611 setPCCPSRDecl = '''
612 CPSR cpsrOrCondCodes = URc;
613 SCTLR sctlr = Sctlr;
614 pNPC = URa;
615 uint32_t newCpsr =
616 cpsrWriteByInstr(cpsrOrCondCodes, URb,
617 0xF, true, sctlr.nmfi);
618 Cpsr = ~CondCodesMask & newCpsr;

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629 'predicate_test': predicateTest},
630 ['IsMicroop'])
631
632 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
633 MicroIntImmDeclare.subst(microSubiUopIop) + \
634 MicroIntRegDeclare.subst(microAddUopIop) + \
635 MicroIntRegDeclare.subst(microSubUopIop) + \
636 MicroIntMovDeclare.subst(microUopRegMovIop) + \
621 setPCCPSRDecl = '''
622 CPSR cpsrOrCondCodes = URc;
623 SCTLR sctlr = Sctlr;
624 pNPC = URa;
625 uint32_t newCpsr =
626 cpsrWriteByInstr(cpsrOrCondCodes, URb,
627 0xF, true, sctlr.nmfi);
628 Cpsr = ~CondCodesMask & newCpsr;

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639 'predicate_test': predicateTest},
640 ['IsMicroop'])
641
642 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
643 MicroIntImmDeclare.subst(microSubiUopIop) + \
644 MicroIntRegDeclare.subst(microAddUopIop) + \
645 MicroIntRegDeclare.subst(microSubUopIop) + \
646 MicroIntMovDeclare.subst(microUopRegMovIop) + \
647 MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
637 MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
638
639 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
640 MicroIntImmConstructor.subst(microSubiUopIop) + \
641 MicroIntRegConstructor.subst(microAddUopIop) + \
642 MicroIntRegConstructor.subst(microSubUopIop) + \
643 MicroIntMovConstructor.subst(microUopRegMovIop) + \
648 MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
649
650 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
651 MicroIntImmConstructor.subst(microSubiUopIop) + \
652 MicroIntRegConstructor.subst(microAddUopIop) + \
653 MicroIntRegConstructor.subst(microSubUopIop) + \
654 MicroIntMovConstructor.subst(microUopRegMovIop) + \
655 MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
644 MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
645
646 exec_output = PredOpExecute.subst(microAddiUopIop) + \
647 PredOpExecute.subst(microSubiUopIop) + \
648 PredOpExecute.subst(microAddUopIop) + \
649 PredOpExecute.subst(microSubUopIop) + \
650 PredOpExecute.subst(microUopRegMovIop) + \
656 MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
657
658 exec_output = PredOpExecute.subst(microAddiUopIop) + \
659 PredOpExecute.subst(microSubiUopIop) + \
660 PredOpExecute.subst(microAddUopIop) + \
661 PredOpExecute.subst(microSubUopIop) + \
662 PredOpExecute.subst(microUopRegMovIop) + \
663 PredOpExecute.subst(microUopRegMovRetIop) + \
651 PredOpExecute.subst(microUopSetPCCPSRIop)
652
653}};
654
655let {{
656 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
657 header_output = MacroMemDeclare.subst(iop)
658 decoder_output = MacroMemConstructor.subst(iop)

--- 21 unchanged lines hidden --- 		664 PredOpExecute.subst(microUopSetPCCPSRIop)
665
666}};
667
668let {{
669 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
670 header_output = MacroMemDeclare.subst(iop)
671 decoder_output = MacroMemConstructor.subst(iop)

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