macromem.isa (7858:ee6641d7c713) macromem.isa (8139:2b2efc67f6df)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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46// Load/store microops
47//
48
49let {{
50 microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
51 microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
52 'MicroMemOp',
53 {'memacc_code': microLdrUopCode,
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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46// Load/store microops
47//
48
49let {{
50 microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
51 microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
52 'MicroMemOp',
53 {'memacc_code': microLdrUopCode,
54 'ea_code': 'EA = Rb + (up ? imm : -imm);',
54 'ea_code': 'EA = URb + (up ? imm : -imm);',
55 'predicate_test': predicateTest},
56 ['IsMicroop'])
57
58 microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
59 microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
60 'MicroMemOp',
61 {'memacc_code': microLdrFpUopCode,
62 'ea_code': vfpEnabledCheckCode +
55 'predicate_test': predicateTest},
56 ['IsMicroop'])
57
58 microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
59 microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
60 'MicroMemOp',
61 {'memacc_code': microLdrFpUopCode,
62 'ea_code': vfpEnabledCheckCode +
63 'EA = Rb + (up ? imm : -imm);',
63 'EA = URb + (up ? imm : -imm);',
64 'predicate_test': predicateTest},
65 ['IsMicroop'])
66
67 microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
68 microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
69 'MicroMemOp',
70 {'memacc_code': microLdrFpUopCode,
71 'ea_code': vfpEnabledCheckCode + '''
64 'predicate_test': predicateTest},
65 ['IsMicroop'])
66
67 microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
68 microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
69 'MicroMemOp',
70 {'memacc_code': microLdrFpUopCode,
71 'ea_code': vfpEnabledCheckCode + '''
72 EA = Rb + (up ? imm : -imm) +
72 EA = URb + (up ? imm : -imm) +
73 (((CPSR)Cpsr).e ? 4 : 0);
74 ''',
75 'predicate_test': predicateTest},
76 ['IsMicroop'])
77
78 microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
79 microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
80 'MicroMemOp',
81 {'memacc_code': microLdrFpUopCode,
82 'ea_code': vfpEnabledCheckCode + '''
73 (((CPSR)Cpsr).e ? 4 : 0);
74 ''',
75 'predicate_test': predicateTest},
76 ['IsMicroop'])
77
78 microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
79 microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
80 'MicroMemOp',
81 {'memacc_code': microLdrFpUopCode,
82 'ea_code': vfpEnabledCheckCode + '''
83 EA = Rb + (up ? imm : -imm) -
83 EA = URb + (up ? imm : -imm) -
84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microLdrRetUopCode = '''
90 CPSR cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;

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96 IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
97 ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
98 | (((CPSR)Spsr).it1 & 0x3);
99 '''
100 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
101 'MicroMemOp',
102 {'memacc_code': microLdrRetUopCode,
103 'ea_code':
84 (((CPSR)Cpsr).e ? 4 : 0);
85 ''',
86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microLdrRetUopCode = '''
90 CPSR cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;

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96 IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
97 ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
98 | (((CPSR)Spsr).it1 & 0x3);
99 '''
100 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
101 'MicroMemOp',
102 {'memacc_code': microLdrRetUopCode,
103 'ea_code':
104 'EA = Rb + (up ? imm : -imm);',
104 'EA = URb + (up ? imm : -imm);',
105 'predicate_test': condPredicateTest},
106 ['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
107
105 'predicate_test': condPredicateTest},
106 ['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
107
108 microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
108 microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
109 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
110 'MicroMemOp',
111 {'memacc_code': microStrUopCode,
112 'postacc_code': "",
109 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
110 'MicroMemOp',
111 {'memacc_code': microStrUopCode,
112 'postacc_code': "",
113 'ea_code': 'EA = Rb + (up ? imm : -imm);',
113 'ea_code': 'EA = URb + (up ? imm : -imm);',
114 'predicate_test': predicateTest},
115 ['IsMicroop'])
116
117 microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
118 microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
119 'MicroMemOp',
120 {'memacc_code': microStrFpUopCode,
121 'postacc_code': "",
122 'ea_code': vfpEnabledCheckCode +
114 'predicate_test': predicateTest},
115 ['IsMicroop'])
116
117 microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
118 microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
119 'MicroMemOp',
120 {'memacc_code': microStrFpUopCode,
121 'postacc_code': "",
122 'ea_code': vfpEnabledCheckCode +
123 'EA = Rb + (up ? imm : -imm);',
123 'EA = URb + (up ? imm : -imm);',
124 'predicate_test': predicateTest},
125 ['IsMicroop'])
126
127 microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
128 microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
129 'MicroMemOp',
130 {'memacc_code': microStrFpUopCode,
131 'postacc_code': "",
132 'ea_code': vfpEnabledCheckCode + '''
124 'predicate_test': predicateTest},
125 ['IsMicroop'])
126
127 microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
128 microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
129 'MicroMemOp',
130 {'memacc_code': microStrFpUopCode,
131 'postacc_code': "",
132 'ea_code': vfpEnabledCheckCode + '''
133 EA = Rb + (up ? imm : -imm) +
133 EA = URb + (up ? imm : -imm) +
134 (((CPSR)Cpsr).e ? 4 : 0);
135 ''',
136 'predicate_test': predicateTest},
137 ['IsMicroop'])
138
139 microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
140 microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
141 'MicroMemOp',
142 {'memacc_code': microStrFpUopCode,
143 'postacc_code': "",
144 'ea_code': vfpEnabledCheckCode + '''
134 (((CPSR)Cpsr).e ? 4 : 0);
135 ''',
136 'predicate_test': predicateTest},
137 ['IsMicroop'])
138
139 microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
140 microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
141 'MicroMemOp',
142 {'memacc_code': microStrFpUopCode,
143 'postacc_code': "",
144 'ea_code': vfpEnabledCheckCode + '''
145 EA = Rb + (up ? imm : -imm) -
145 EA = URb + (up ? imm : -imm) -
146 (((CPSR)Cpsr).e ? 4 : 0);
147 ''',
148 'predicate_test': predicateTest},
149 ['IsMicroop'])
150
151 header_output = decoder_output = exec_output = ''
152
153 loadIops = (microLdrUopIop, microLdrRetUopIop,

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165 exec_output += StoreExecute.subst(iop) + \
166 StoreInitiateAcc.subst(iop) + \
167 StoreCompleteAcc.subst(iop)
168}};
169
170let {{
171 exec_output = header_output = ''
172
146 (((CPSR)Cpsr).e ? 4 : 0);
147 ''',
148 'predicate_test': predicateTest},
149 ['IsMicroop'])
150
151 header_output = decoder_output = exec_output = ''
152
153 loadIops = (microLdrUopIop, microLdrRetUopIop,

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165 exec_output += StoreExecute.subst(iop) + \
166 StoreInitiateAcc.subst(iop) + \
167 StoreCompleteAcc.subst(iop)
168}};
169
170let {{
171 exec_output = header_output = ''
172
173 eaCode = 'EA = Ra + imm;'
173 eaCode = 'EA = URa + imm;'
174
175 for size in (1, 2, 3, 4, 6, 8, 12, 16):
176 # Set up the memory access.
177 regs = (size + 3) // 4
178 subst = { "size" : size, "regs" : regs }
179 memDecl = '''
180 union MemUnion {
181 uint8_t bytes[%(size)d];

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567////////////////////////////////////////////////////////////////////
568//
569// Integer = Integer op Immediate microops
570//
571
572let {{
573 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
574 'MicroIntImmOp',
174
175 for size in (1, 2, 3, 4, 6, 8, 12, 16):
176 # Set up the memory access.
177 regs = (size + 3) // 4
178 subst = { "size" : size, "regs" : regs }
179 memDecl = '''
180 union MemUnion {
181 uint8_t bytes[%(size)d];

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567////////////////////////////////////////////////////////////////////
568//
569// Integer = Integer op Immediate microops
570//
571
572let {{
573 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
574 'MicroIntImmOp',
575 {'code': 'Ra = Rb + imm;',
575 {'code': 'URa = URb + imm;',
576 'predicate_test': predicateTest},
577 ['IsMicroop'])
578
579 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
580 'MicroIntRegOp',
581 {'code':
576 'predicate_test': predicateTest},
577 ['IsMicroop'])
578
579 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
580 'MicroIntRegOp',
581 {'code':
582 '''Ra = Rb + shift_rm_imm(Rc, shiftAmt,
582 '''URa = URb + shift_rm_imm(URc, shiftAmt,
583 shiftType,
584 CondCodes<29:>);
585 ''',
586 'predicate_test': predicateTest},
587 ['IsMicroop'])
588
589 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
590 'MicroIntImmOp',
583 shiftType,
584 CondCodes<29:>);
585 ''',
586 'predicate_test': predicateTest},
587 ['IsMicroop'])
588
589 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
590 'MicroIntImmOp',
591 {'code': 'Ra = Rb - imm;',
591 {'code': 'URa = URb - imm;',
592 'predicate_test': predicateTest},
593 ['IsMicroop'])
594
595 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
596 'MicroIntRegOp',
597 {'code':
592 'predicate_test': predicateTest},
593 ['IsMicroop'])
594
595 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
596 'MicroIntRegOp',
597 {'code':
598 '''Ra = Rb - shift_rm_imm(Rc, shiftAmt,
598 '''URa = URb - shift_rm_imm(URc, shiftAmt,
599 shiftType,
600 CondCodes<29:>);
601 ''',
602 'predicate_test': predicateTest},
603 ['IsMicroop'])
604
605 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
606 'MicroIntMov',
599 shiftType,
600 CondCodes<29:>);
601 ''',
602 'predicate_test': predicateTest},
603 ['IsMicroop'])
604
605 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
606 'MicroIntMov',
607 {'code': 'IWRa = Rb;',
607 {'code': 'IWRa = URb;',
608 'predicate_test': predicateTest},
609 ['IsMicroop'])
610
611 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
612 MicroIntImmDeclare.subst(microSubiUopIop) + \
613 MicroIntRegDeclare.subst(microAddUopIop) + \
614 MicroIntRegDeclare.subst(microSubUopIop) + \
615 MicroIntMovDeclare.subst(microUopRegMovIop)

--- 39 unchanged lines hidden --- 		608 'predicate_test': predicateTest},
609 ['IsMicroop'])
610
611 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
612 MicroIntImmDeclare.subst(microSubiUopIop) + \
613 MicroIntRegDeclare.subst(microAddUopIop) + \
614 MicroIntRegDeclare.subst(microSubUopIop) + \
615 MicroIntMovDeclare.subst(microUopRegMovIop)

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