macromem.isa (7644:62873d5c2bfc) macromem.isa (7646:a444dbee8c07)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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570let {{
571 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
572 'MicroIntImmOp',
573 {'code': 'Ra = Rb + imm;',
574 'predicate_test': predicateTest},
575 ['IsMicroop'])
576
577 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 561 unchanged lines hidden (view full) ---

570let {{
571 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
572 'MicroIntImmOp',
573 {'code': 'Ra = Rb + imm;',
574 'predicate_test': predicateTest},
575 ['IsMicroop'])
576
577 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
578 'MicroIntOp',
579 {'code': 'Ra = Rb + Rc;',
578 'MicroIntRegOp',
579 {'code':
580 '''Ra = Rb + shift_rm_imm(Rc, shiftAmt,
581 shiftType,
582 CondCodes<29:>);
583 ''',
580 'predicate_test': predicateTest},
581 ['IsMicroop'])
582
583 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
584 'MicroIntImmOp',
585 {'code': 'Ra = Rb - imm;',
586 'predicate_test': predicateTest},
587 ['IsMicroop'])
588
584 'predicate_test': predicateTest},
585 ['IsMicroop'])
586
587 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
588 'MicroIntImmOp',
589 {'code': 'Ra = Rb - imm;',
590 'predicate_test': predicateTest},
591 ['IsMicroop'])
592
593 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
594 'MicroIntRegOp',
595 {'code':
596 '''Ra = Rb - shift_rm_imm(Rc, shiftAmt,
597 shiftType,
598 CondCodes<29:>);
599 ''',
600 'predicate_test': predicateTest},
601 ['IsMicroop'])
602
603 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
604 'MicroIntMov',
605 {'code': 'IWRa = Rb;',
606 'predicate_test': predicateTest},
607 ['IsMicroop'])
608
589 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
590 MicroIntImmDeclare.subst(microSubiUopIop) + \
609 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
610 MicroIntImmDeclare.subst(microSubiUopIop) + \
591 MicroIntDeclare.subst(microAddUopIop)
611 MicroIntRegDeclare.subst(microAddUopIop) + \
612 MicroIntRegDeclare.subst(microSubUopIop) + \
613 MicroIntMovDeclare.subst(microUopRegMovIop)
614
592 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
593 MicroIntImmConstructor.subst(microSubiUopIop) + \
615 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
616 MicroIntImmConstructor.subst(microSubiUopIop) + \
594 MicroIntConstructor.subst(microAddUopIop)
617 MicroIntRegConstructor.subst(microAddUopIop) + \
618 MicroIntRegConstructor.subst(microSubUopIop) + \
619 MicroIntMovConstructor.subst(microUopRegMovIop)
620
595 exec_output = PredOpExecute.subst(microAddiUopIop) + \
596 PredOpExecute.subst(microSubiUopIop) + \
621 exec_output = PredOpExecute.subst(microAddiUopIop) + \
622 PredOpExecute.subst(microSubiUopIop) + \
597 PredOpExecute.subst(microAddUopIop)
623 PredOpExecute.subst(microAddUopIop) + \
624 PredOpExecute.subst(microSubUopIop) + \
625 PredOpExecute.subst(microUopRegMovIop)
598}};
599
600let {{
601 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
602 header_output = MacroMemDeclare.subst(iop)
603 decoder_output = MacroMemConstructor.subst(iop)
604
605 iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])

--- 19 unchanged lines hidden --- 		626}};
627
628let {{
629 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
630 header_output = MacroMemDeclare.subst(iop)
631 decoder_output = MacroMemConstructor.subst(iop)
632
633 iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])

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