macromem.isa (7342:72166bc39ff8) | macromem.isa (7400:f6c9b27c4dbe) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 55 unchanged lines hidden (view full) --- 64 'MicroMemOp', 65 {'memacc_code': microLdrFpUopCode, 66 'ea_code': 'EA = Rb + (up ? imm : -imm);', 67 'predicate_test': predicateTest}, 68 ['IsMicroop']) 69 70 microLdrRetUopCode = ''' 71 CPSR cpsr = Cpsr; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 55 unchanged lines hidden (view full) --- 64 'MicroMemOp', 65 {'memacc_code': microLdrFpUopCode, 66 'ea_code': 'EA = Rb + (up ? imm : -imm);', 67 'predicate_test': predicateTest}, 68 ['IsMicroop']) 69 70 microLdrRetUopCode = ''' 71 CPSR cpsr = Cpsr; |
72 SCTLR sctlr = Sctlr; |
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72 uint32_t newCpsr = | 73 uint32_t newCpsr = |
73 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true); | 74 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); |
74 Cpsr = ~CondCodesMask & newCpsr; 75 CondCodes = CondCodesMask & newCpsr; 76 IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); 77 ''' 78 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 79 'MicroMemOp', 80 {'memacc_code': microLdrRetUopCode, 81 'ea_code': --- 74 unchanged lines hidden --- | 75 Cpsr = ~CondCodesMask & newCpsr; 76 CondCodes = CondCodesMask & newCpsr; 77 IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); 78 ''' 79 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 80 'MicroMemOp', 81 {'memacc_code': microLdrRetUopCode, 82 'ea_code': --- 74 unchanged lines hidden --- |