1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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86 'predicate_test': predicateTest},
87 ['IsMicroop'])
88
89 microRetUopCode = '''
90 CPSR old_cpsr = Cpsr;
91 SCTLR sctlr = Sctlr;
92
93 CPSR new_cpsr =
94 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
95 Cpsr = ~CondCodesMask & new_cpsr;
96 CondCodesNZ = new_cpsr.nz;
97 CondCodesC = new_cpsr.c;
98 CondCodesV = new_cpsr.v;
99 CondCodesGE = new_cpsr.ge;
100 IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
101 NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
102 | (((CPSR)Spsr).it1 & 0x3);

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153 EA = URb + (up ? imm : -imm) -
154 (((CPSR)Cpsr).e ? 4 : 0);
155 ''',
156 'predicate_test': predicateTest},
157 ['IsMicroop'])
158
159 header_output = decoder_output = exec_output = ''
160
161 loadIops = (microLdrUopIop, microLdrRetUopIop,
162 microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop)
163 storeIops = (microStrUopIop, microStrFpUopIop,
164 microStrDBFpUopIop, microStrDTFpUopIop)
165 for iop in loadIops + storeIops:
166 header_output += MicroMemDeclare.subst(iop)
167 decoder_output += MicroMemConstructor.subst(iop)
168 for iop in loadIops:
169 exec_output += LoadExecute.subst(iop) + \
170 LoadInitiateAcc.subst(iop) + \
171 LoadCompleteAcc.subst(iop)
172 for iop in storeIops:
173 exec_output += StoreExecute.subst(iop) + \
174 StoreInitiateAcc.subst(iop) + \
175 StoreCompleteAcc.subst(iop)
176}};
177
178let {{
179 exec_output = header_output = ''
180
181 eaCode = 'EA = URa + imm;'
182
183 for size in (1, 2, 3, 4, 6, 8, 12, 16):
184 # Set up the memory access.
185 regs = (size + 3) // 4
186 subst = { "size" : size, "regs" : regs }
187 memDecl = '''
188 union MemUnion {
189 uint8_t bytes[%(size)d];

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587 {'code': 'URa = URb + imm;',
588 'predicate_test': predicateTest},
589 ['IsMicroop'])
590
591 microAddUopCode = '''
592 URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
593 '''
594
595 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
596 'MicroIntRegOp',
597 {'code': microAddUopCode,
598 'predicate_test': pickPredicate(microAddUopCode)},
599 ['IsMicroop'])
600
601 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
602 'MicroIntImmOp',
603 {'code': 'URa = URb - imm;',
604 'predicate_test': predicateTest},
605 ['IsMicroop'])
606
607 microSubUopCode = '''
608 URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
609 '''
610 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
611 'MicroIntRegOp',
612 {'code': microSubUopCode,
613 'predicate_test': pickPredicate(microSubUopCode)},
614 ['IsMicroop'])

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626 ['IsMicroop', 'IsNonSpeculative',
627 'IsSerializeAfter'])
628
629 setPCCPSRDecl = '''
630 CPSR cpsrOrCondCodes = URc;
631 SCTLR sctlr = Sctlr;
632 pNPC = URa;
633 CPSR new_cpsr =
634 cpsrWriteByInstr(cpsrOrCondCodes, URb,
635 0xF, true, sctlr.nmfi);
636 Cpsr = ~CondCodesMask & new_cpsr;
637 NextThumb = new_cpsr.t;
638 NextJazelle = new_cpsr.j;
639 NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
640 | (((CPSR)URb).it1 & 0x3);
641 CondCodesNZ = new_cpsr.nz;
642 CondCodesC = new_cpsr.c;
643 CondCodesV = new_cpsr.v;
644 CondCodesGE = new_cpsr.ge;
645 '''
646
647 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
648 'MicroSetPCCPSR',
649 {'code': setPCCPSRDecl,
650 'predicate_test': predicateTest},
651 ['IsMicroop'])
652
653 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
654 MicroIntImmDeclare.subst(microSubiUopIop) + \
655 MicroIntRegDeclare.subst(microAddUopIop) + \
656 MicroIntRegDeclare.subst(microSubUopIop) + \
657 MicroIntMovDeclare.subst(microUopRegMovIop) + \
658 MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
659 MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
660
661 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
662 MicroIntImmConstructor.subst(microSubiUopIop) + \
663 MicroIntRegConstructor.subst(microAddUopIop) + \
664 MicroIntRegConstructor.subst(microSubUopIop) + \
665 MicroIntMovConstructor.subst(microUopRegMovIop) + \
666 MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
667 MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
668
669 exec_output = PredOpExecute.subst(microAddiUopIop) + \
670 PredOpExecute.subst(microSubiUopIop) + \
671 PredOpExecute.subst(microAddUopIop) + \
672 PredOpExecute.subst(microSubUopIop) + \
673 PredOpExecute.subst(microUopRegMovIop) + \
674 PredOpExecute.subst(microUopRegMovRetIop) + \
675 PredOpExecute.subst(microUopSetPCCPSRIop)
676
677}};
678
679let {{
680 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
681 header_output = MacroMemDeclare.subst(iop)
682 decoder_output = MacroMemConstructor.subst(iop)
683
684 iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
685 header_output += VMemMultDeclare.subst(iop)
686 decoder_output += VMemMultConstructor.subst(iop)
687
688 iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
689 header_output += VMemSingleDeclare.subst(iop)
690 decoder_output += VMemSingleConstructor.subst(iop)
691

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