1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gene Wu
38
39
40let {{
41 header_output = ""
42 decoder_output = '''
43 uint64_t join32to64(uint32_t r1, uint32_t r0)
44 {
45 uint64_t r = r1;
46 r <<= 32;
47 r |= r0;
48 return r;
49 }
50 '''
51 exec_output = '''
52 uint64_t join32to64(uint32_t r1, uint32_t r0);
53 '''
54
55
56 armCode = '''
57 PseudoInst::arm(xc->tcBase());
58 '''
59 armIop = InstObjParams("arm", "Arm", "PredOp",
60 { "code": armCode,
61 "predicate_test": predicateTest },
62 ["IsNonSpeculative"])
63 header_output += BasicDeclare.subst(armIop)
64 decoder_output += BasicConstructor.subst(armIop)
65 exec_output += PredOpExecute.subst(armIop)
66
67 quiesceCode = '''
68 PseudoInst::quiesce(xc->tcBase());
69 '''
70 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
71 { "code": quiesceCode,
72 "predicate_test": predicateTest },
73 ["IsNonSpeculative", "IsQuiesce"])
74 header_output += BasicDeclare.subst(quiesceIop)
75 decoder_output += BasicConstructor.subst(quiesceIop)
76 exec_output += QuiescePredOpExecute.subst(quiesceIop)
77
78 quiesceNsCode = '''
79 PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
80 '''
81
82 quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
83 { "code": quiesceNsCode,
84 "predicate_test": predicateTest },
85 ["IsNonSpeculative", "IsQuiesce"])
86 header_output += BasicDeclare.subst(quiesceNsIop)
87 decoder_output += BasicConstructor.subst(quiesceNsIop)
88 exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
89
90 quiesceCyclesCode = '''
91 PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
92 '''
93
94 quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
95 { "code": quiesceCyclesCode,
96 "predicate_test": predicateTest },
97 ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
98 header_output += BasicDeclare.subst(quiesceCyclesIop)
99 decoder_output += BasicConstructor.subst(quiesceCyclesIop)
100 exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
101
102 quiesceTimeCode = '''
103 uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
104 R0 = bits(qt_val, 31, 0);
105 R1 = bits(qt_val, 63, 32);
106 '''
107
108 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
109 { "code": quiesceTimeCode,
110 "predicate_test": predicateTest },
111 ["IsNonSpeculative", "IsUnverifiable"])
112 header_output += BasicDeclare.subst(quiesceTimeIop)
113 decoder_output += BasicConstructor.subst(quiesceTimeIop)
114 exec_output += PredOpExecute.subst(quiesceTimeIop)
115
116 rpnsCode = '''
117 uint64_t rpns_val = PseudoInst::rpns(xc->tcBase());
118 R0 = bits(rpns_val, 31, 0);
119 R1 = bits(rpns_val, 63, 32);
120 '''
121
122 rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
123 { "code": rpnsCode,
124 "predicate_test": predicateTest },
125 ["IsNonSpeculative", "IsUnverifiable"])
126 header_output += BasicDeclare.subst(rpnsIop)
127 decoder_output += BasicConstructor.subst(rpnsIop)
128 exec_output += PredOpExecute.subst(rpnsIop)
129
130 wakeCpuCode = '''
131 PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0));
132 '''
133
134 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
135 { "code": wakeCpuCode,
136 "predicate_test": predicateTest },
137 ["IsNonSpeculative", "IsUnverifiable"])
138 header_output += BasicDeclare.subst(wakeCPUIop)
139 decoder_output += BasicConstructor.subst(wakeCPUIop)
140 exec_output += PredOpExecute.subst(wakeCPUIop)
141
142 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp",
143 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''',
144 "predicate_test": predicateTest })
145 header_output += BasicDeclare.subst(deprecated_ivlbIop)
146 decoder_output += BasicConstructor.subst(deprecated_ivlbIop)
147 exec_output += PredOpExecute.subst(deprecated_ivlbIop)
148
149 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp",
150 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''',
151 "predicate_test": predicateTest })
152 header_output += BasicDeclare.subst(deprecated_ivleIop)
153 decoder_output += BasicConstructor.subst(deprecated_ivleIop)
154 exec_output += PredOpExecute.subst(deprecated_ivleIop)
155
156 deprecated_exit_code = '''
157 warn_once("Obsolete M5 exit instruction encountered.\\n");
158 PseudoInst::m5exit(xc->tcBase(), 0);
159 '''
160
161 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp",
162 { "code": deprecated_exit_code,
163 "predicate_test": predicateTest },
164 ["No_OpClass", "IsNonSpeculative"])
165 header_output += BasicDeclare.subst(deprecated_exitIop)
166 decoder_output += BasicConstructor.subst(deprecated_exitIop)
167 exec_output += PredOpExecute.subst(deprecated_exitIop)
168
169 m5exit_code = '''
170 PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0));
171 '''
172 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
173 { "code": m5exit_code,
174 "predicate_test": predicateTest },
175 ["No_OpClass", "IsNonSpeculative"])
176 header_output += BasicDeclare.subst(m5exitIop)
177 decoder_output += BasicConstructor.subst(m5exitIop)
178 exec_output += PredOpExecute.subst(m5exitIop)
179
180 loadsymbolCode = '''
181 PseudoInst::loadsymbol(xc->tcBase());
182 '''
183
184 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
185 { "code": loadsymbolCode,
186 "predicate_test": predicateTest },
187 ["No_OpClass", "IsNonSpeculative"])
188 header_output += BasicDeclare.subst(loadsymbolIop)
189 decoder_output += BasicConstructor.subst(loadsymbolIop)
190 exec_output += PredOpExecute.subst(loadsymbolIop)
191
192 initparamCode = '''
| 1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gene Wu
38
39
40let {{
41 header_output = ""
42 decoder_output = '''
43 uint64_t join32to64(uint32_t r1, uint32_t r0)
44 {
45 uint64_t r = r1;
46 r <<= 32;
47 r |= r0;
48 return r;
49 }
50 '''
51 exec_output = '''
52 uint64_t join32to64(uint32_t r1, uint32_t r0);
53 '''
54
55
56 armCode = '''
57 PseudoInst::arm(xc->tcBase());
58 '''
59 armIop = InstObjParams("arm", "Arm", "PredOp",
60 { "code": armCode,
61 "predicate_test": predicateTest },
62 ["IsNonSpeculative"])
63 header_output += BasicDeclare.subst(armIop)
64 decoder_output += BasicConstructor.subst(armIop)
65 exec_output += PredOpExecute.subst(armIop)
66
67 quiesceCode = '''
68 PseudoInst::quiesce(xc->tcBase());
69 '''
70 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
71 { "code": quiesceCode,
72 "predicate_test": predicateTest },
73 ["IsNonSpeculative", "IsQuiesce"])
74 header_output += BasicDeclare.subst(quiesceIop)
75 decoder_output += BasicConstructor.subst(quiesceIop)
76 exec_output += QuiescePredOpExecute.subst(quiesceIop)
77
78 quiesceNsCode = '''
79 PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
80 '''
81
82 quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
83 { "code": quiesceNsCode,
84 "predicate_test": predicateTest },
85 ["IsNonSpeculative", "IsQuiesce"])
86 header_output += BasicDeclare.subst(quiesceNsIop)
87 decoder_output += BasicConstructor.subst(quiesceNsIop)
88 exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
89
90 quiesceCyclesCode = '''
91 PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
92 '''
93
94 quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
95 { "code": quiesceCyclesCode,
96 "predicate_test": predicateTest },
97 ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
98 header_output += BasicDeclare.subst(quiesceCyclesIop)
99 decoder_output += BasicConstructor.subst(quiesceCyclesIop)
100 exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
101
102 quiesceTimeCode = '''
103 uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
104 R0 = bits(qt_val, 31, 0);
105 R1 = bits(qt_val, 63, 32);
106 '''
107
108 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
109 { "code": quiesceTimeCode,
110 "predicate_test": predicateTest },
111 ["IsNonSpeculative", "IsUnverifiable"])
112 header_output += BasicDeclare.subst(quiesceTimeIop)
113 decoder_output += BasicConstructor.subst(quiesceTimeIop)
114 exec_output += PredOpExecute.subst(quiesceTimeIop)
115
116 rpnsCode = '''
117 uint64_t rpns_val = PseudoInst::rpns(xc->tcBase());
118 R0 = bits(rpns_val, 31, 0);
119 R1 = bits(rpns_val, 63, 32);
120 '''
121
122 rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
123 { "code": rpnsCode,
124 "predicate_test": predicateTest },
125 ["IsNonSpeculative", "IsUnverifiable"])
126 header_output += BasicDeclare.subst(rpnsIop)
127 decoder_output += BasicConstructor.subst(rpnsIop)
128 exec_output += PredOpExecute.subst(rpnsIop)
129
130 wakeCpuCode = '''
131 PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0));
132 '''
133
134 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
135 { "code": wakeCpuCode,
136 "predicate_test": predicateTest },
137 ["IsNonSpeculative", "IsUnverifiable"])
138 header_output += BasicDeclare.subst(wakeCPUIop)
139 decoder_output += BasicConstructor.subst(wakeCPUIop)
140 exec_output += PredOpExecute.subst(wakeCPUIop)
141
142 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp",
143 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''',
144 "predicate_test": predicateTest })
145 header_output += BasicDeclare.subst(deprecated_ivlbIop)
146 decoder_output += BasicConstructor.subst(deprecated_ivlbIop)
147 exec_output += PredOpExecute.subst(deprecated_ivlbIop)
148
149 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp",
150 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''',
151 "predicate_test": predicateTest })
152 header_output += BasicDeclare.subst(deprecated_ivleIop)
153 decoder_output += BasicConstructor.subst(deprecated_ivleIop)
154 exec_output += PredOpExecute.subst(deprecated_ivleIop)
155
156 deprecated_exit_code = '''
157 warn_once("Obsolete M5 exit instruction encountered.\\n");
158 PseudoInst::m5exit(xc->tcBase(), 0);
159 '''
160
161 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp",
162 { "code": deprecated_exit_code,
163 "predicate_test": predicateTest },
164 ["No_OpClass", "IsNonSpeculative"])
165 header_output += BasicDeclare.subst(deprecated_exitIop)
166 decoder_output += BasicConstructor.subst(deprecated_exitIop)
167 exec_output += PredOpExecute.subst(deprecated_exitIop)
168
169 m5exit_code = '''
170 PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0));
171 '''
172 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
173 { "code": m5exit_code,
174 "predicate_test": predicateTest },
175 ["No_OpClass", "IsNonSpeculative"])
176 header_output += BasicDeclare.subst(m5exitIop)
177 decoder_output += BasicConstructor.subst(m5exitIop)
178 exec_output += PredOpExecute.subst(m5exitIop)
179
180 loadsymbolCode = '''
181 PseudoInst::loadsymbol(xc->tcBase());
182 '''
183
184 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
185 { "code": loadsymbolCode,
186 "predicate_test": predicateTest },
187 ["No_OpClass", "IsNonSpeculative"])
188 header_output += BasicDeclare.subst(loadsymbolIop)
189 decoder_output += BasicConstructor.subst(loadsymbolIop)
190 exec_output += PredOpExecute.subst(loadsymbolIop)
191
192 initparamCode = '''
|
199 header_output += BasicDeclare.subst(initparamIop)
200 decoder_output += BasicConstructor.subst(initparamIop)
201 exec_output += PredOpExecute.subst(initparamIop)
202
203 resetstats_code = '''
204 PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
205 '''
206
207 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
208 { "code": resetstats_code,
209 "predicate_test": predicateTest },
210 ["IsNonSpeculative"])
211 header_output += BasicDeclare.subst(resetstatsIop)
212 decoder_output += BasicConstructor.subst(resetstatsIop)
213 exec_output += PredOpExecute.subst(resetstatsIop)
214
215 dumpstats_code = '''
216 PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
217 '''
218 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
219 { "code": dumpstats_code,
220 "predicate_test": predicateTest },
221 ["IsNonSpeculative"])
222 header_output += BasicDeclare.subst(dumpstatsIop)
223 decoder_output += BasicConstructor.subst(dumpstatsIop)
224 exec_output += PredOpExecute.subst(dumpstatsIop)
225
226 dumpresetstats_code = '''
227 PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
228 '''
229 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
230 { "code": dumpresetstats_code,
231 "predicate_test": predicateTest },
232 ["IsNonSpeculative"])
233 header_output += BasicDeclare.subst(dumpresetstatsIop)
234 decoder_output += BasicConstructor.subst(dumpresetstatsIop)
235 exec_output += PredOpExecute.subst(dumpresetstatsIop)
236
237 m5checkpoint_code = '''
238 PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
239 '''
240 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
241 { "code": m5checkpoint_code,
242 "predicate_test": predicateTest },
243 ["IsNonSpeculative"])
244 header_output += BasicDeclare.subst(m5checkpointIop)
245 decoder_output += BasicConstructor.subst(m5checkpointIop)
246 exec_output += PredOpExecute.subst(m5checkpointIop)
247
248 m5readfileCode = '''
249 int n = 4;
250 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
251 R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
252 '''
253 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
254 { "code": m5readfileCode,
255 "predicate_test": predicateTest },
256 ["IsNonSpeculative"])
257 header_output += BasicDeclare.subst(m5readfileIop)
258 decoder_output += BasicConstructor.subst(m5readfileIop)
259 exec_output += PredOpExecute.subst(m5readfileIop)
260
261 m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
262 { "code": "PseudoInst::debugbreak(xc->tcBase());",
263 "predicate_test": predicateTest },
264 ["IsNonSpeculative"])
265 header_output += BasicDeclare.subst(m5breakIop)
266 decoder_output += BasicConstructor.subst(m5breakIop)
267 exec_output += PredOpExecute.subst(m5breakIop)
268
269 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp",
270 { "code": "PseudoInst::switchcpu(xc->tcBase());",
271 "predicate_test": predicateTest },
272 ["IsNonSpeculative"])
273 header_output += BasicDeclare.subst(m5switchcpuIop)
274 decoder_output += BasicConstructor.subst(m5switchcpuIop)
275 exec_output += PredOpExecute.subst(m5switchcpuIop)
276
277 m5addsymbolCode = '''
278 PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
279 '''
280 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
281 { "code": m5addsymbolCode,
282 "predicate_test": predicateTest },
283 ["IsNonSpeculative"])
284 header_output += BasicDeclare.subst(m5addsymbolIop)
285 decoder_output += BasicConstructor.subst(m5addsymbolIop)
286 exec_output += PredOpExecute.subst(m5addsymbolIop)
287
288 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
289 xc->pcState().pc());'''
290 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp",
291 { "code": m5panicCode,
292 "predicate_test": predicateTest },
293 ["IsNonSpeculative"])
294 header_output += BasicDeclare.subst(m5panicIop)
295 decoder_output += BasicConstructor.subst(m5panicIop)
296 exec_output += PredOpExecute.subst(m5panicIop)
297
298 m5workbeginCode = '''PseudoInst::workbegin(
299 xc->tcBase(),
300 join32to64(R1, R0),
301 join32to64(R3, R2)
302 );'''
303 m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp",
304 { "code": m5workbeginCode,
305 "predicate_test": predicateTest },
306 ["IsNonSpeculative"])
307 header_output += BasicDeclare.subst(m5workbeginIop)
308 decoder_output += BasicConstructor.subst(m5workbeginIop)
309 exec_output += PredOpExecute.subst(m5workbeginIop)
310
311 m5workendCode = '''PseudoInst::workend(
312 xc->tcBase(),
313 join32to64(R1, R0),
314 join32to64(R3, R2)
315 );'''
316 m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp",
317 { "code": m5workendCode,
318 "predicate_test": predicateTest },
319 ["IsNonSpeculative"])
320 header_output += BasicDeclare.subst(m5workendIop)
321 decoder_output += BasicConstructor.subst(m5workendIop)
322 exec_output += PredOpExecute.subst(m5workendIop)
323
324}};
| 202 header_output += BasicDeclare.subst(initparamIop)
203 decoder_output += BasicConstructor.subst(initparamIop)
204 exec_output += PredOpExecute.subst(initparamIop)
205
206 resetstats_code = '''
207 PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
208 '''
209
210 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
211 { "code": resetstats_code,
212 "predicate_test": predicateTest },
213 ["IsNonSpeculative"])
214 header_output += BasicDeclare.subst(resetstatsIop)
215 decoder_output += BasicConstructor.subst(resetstatsIop)
216 exec_output += PredOpExecute.subst(resetstatsIop)
217
218 dumpstats_code = '''
219 PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
220 '''
221 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
222 { "code": dumpstats_code,
223 "predicate_test": predicateTest },
224 ["IsNonSpeculative"])
225 header_output += BasicDeclare.subst(dumpstatsIop)
226 decoder_output += BasicConstructor.subst(dumpstatsIop)
227 exec_output += PredOpExecute.subst(dumpstatsIop)
228
229 dumpresetstats_code = '''
230 PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
231 '''
232 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
233 { "code": dumpresetstats_code,
234 "predicate_test": predicateTest },
235 ["IsNonSpeculative"])
236 header_output += BasicDeclare.subst(dumpresetstatsIop)
237 decoder_output += BasicConstructor.subst(dumpresetstatsIop)
238 exec_output += PredOpExecute.subst(dumpresetstatsIop)
239
240 m5checkpoint_code = '''
241 PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
242 '''
243 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
244 { "code": m5checkpoint_code,
245 "predicate_test": predicateTest },
246 ["IsNonSpeculative"])
247 header_output += BasicDeclare.subst(m5checkpointIop)
248 decoder_output += BasicConstructor.subst(m5checkpointIop)
249 exec_output += PredOpExecute.subst(m5checkpointIop)
250
251 m5readfileCode = '''
252 int n = 4;
253 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
254 R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
255 '''
256 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
257 { "code": m5readfileCode,
258 "predicate_test": predicateTest },
259 ["IsNonSpeculative"])
260 header_output += BasicDeclare.subst(m5readfileIop)
261 decoder_output += BasicConstructor.subst(m5readfileIop)
262 exec_output += PredOpExecute.subst(m5readfileIop)
263
264 m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
265 { "code": "PseudoInst::debugbreak(xc->tcBase());",
266 "predicate_test": predicateTest },
267 ["IsNonSpeculative"])
268 header_output += BasicDeclare.subst(m5breakIop)
269 decoder_output += BasicConstructor.subst(m5breakIop)
270 exec_output += PredOpExecute.subst(m5breakIop)
271
272 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp",
273 { "code": "PseudoInst::switchcpu(xc->tcBase());",
274 "predicate_test": predicateTest },
275 ["IsNonSpeculative"])
276 header_output += BasicDeclare.subst(m5switchcpuIop)
277 decoder_output += BasicConstructor.subst(m5switchcpuIop)
278 exec_output += PredOpExecute.subst(m5switchcpuIop)
279
280 m5addsymbolCode = '''
281 PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
282 '''
283 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
284 { "code": m5addsymbolCode,
285 "predicate_test": predicateTest },
286 ["IsNonSpeculative"])
287 header_output += BasicDeclare.subst(m5addsymbolIop)
288 decoder_output += BasicConstructor.subst(m5addsymbolIop)
289 exec_output += PredOpExecute.subst(m5addsymbolIop)
290
291 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
292 xc->pcState().pc());'''
293 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp",
294 { "code": m5panicCode,
295 "predicate_test": predicateTest },
296 ["IsNonSpeculative"])
297 header_output += BasicDeclare.subst(m5panicIop)
298 decoder_output += BasicConstructor.subst(m5panicIop)
299 exec_output += PredOpExecute.subst(m5panicIop)
300
301 m5workbeginCode = '''PseudoInst::workbegin(
302 xc->tcBase(),
303 join32to64(R1, R0),
304 join32to64(R3, R2)
305 );'''
306 m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp",
307 { "code": m5workbeginCode,
308 "predicate_test": predicateTest },
309 ["IsNonSpeculative"])
310 header_output += BasicDeclare.subst(m5workbeginIop)
311 decoder_output += BasicConstructor.subst(m5workbeginIop)
312 exec_output += PredOpExecute.subst(m5workbeginIop)
313
314 m5workendCode = '''PseudoInst::workend(
315 xc->tcBase(),
316 join32to64(R1, R0),
317 join32to64(R3, R2)
318 );'''
319 m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp",
320 { "code": m5workendCode,
321 "predicate_test": predicateTest },
322 ["IsNonSpeculative"])
323 header_output += BasicDeclare.subst(m5workendIop)
324 decoder_output += BasicConstructor.subst(m5workendIop)
325 exec_output += PredOpExecute.subst(m5workendIop)
326
327}};
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