1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gene Wu
38
39
40let {{
41 header_output = ""
42 decoder_output = ""
43 exec_output = ""
44
45 armCode = '''
46#if FULL_SYSTEM
47 PseudoInst::arm(xc->tcBase());
48#endif
49 '''
50 armIop = InstObjParams("arm", "Arm", "PredOp",
51 { "code": armCode,
52 "predicate_test": predicateTest },
53 ["IsNonSpeculative"])
54 header_output += BasicDeclare.subst(armIop)
55 decoder_output += BasicConstructor.subst(armIop)
56 exec_output += PredOpExecute.subst(armIop)
57
58 quiesceCode = '''
59#if FULL_SYSTEM
60 PseudoInst::quiesceNs(xc->tcBase(), R0);
61#endif
62 '''
63 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
64 { "code": quiesceCode,
65 "predicate_test": predicateTest },
66 ["IsNonSpeculative", "IsQuiesce"])
67 header_output += BasicDeclare.subst(quiesceIop)
68 decoder_output += BasicConstructor.subst(quiesceIop)
| 1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gene Wu
38
39
40let {{
41 header_output = ""
42 decoder_output = ""
43 exec_output = ""
44
45 armCode = '''
46#if FULL_SYSTEM
47 PseudoInst::arm(xc->tcBase());
48#endif
49 '''
50 armIop = InstObjParams("arm", "Arm", "PredOp",
51 { "code": armCode,
52 "predicate_test": predicateTest },
53 ["IsNonSpeculative"])
54 header_output += BasicDeclare.subst(armIop)
55 decoder_output += BasicConstructor.subst(armIop)
56 exec_output += PredOpExecute.subst(armIop)
57
58 quiesceCode = '''
59#if FULL_SYSTEM
60 PseudoInst::quiesceNs(xc->tcBase(), R0);
61#endif
62 '''
63 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
64 { "code": quiesceCode,
65 "predicate_test": predicateTest },
66 ["IsNonSpeculative", "IsQuiesce"])
67 header_output += BasicDeclare.subst(quiesceIop)
68 decoder_output += BasicConstructor.subst(quiesceIop)
|
98
99 quiesceTimeCode = '''
100#if FULL_SYSTEM
101 R0 = PseudoInst::quiesceTime(xc->tcBase());
102#endif
103 '''
104
105 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
106 { "code": quiesceTimeCode,
107 "predicate_test": predicateTest },
108 ["IsNonSpeculative", "IsUnverifiable"])
109 header_output += BasicDeclare.subst(quiesceTimeIop)
110 decoder_output += BasicConstructor.subst(quiesceTimeIop)
111 exec_output += PredOpExecute.subst(quiesceTimeIop)
112
113 rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
114 { "code": "R0 = PseudoInst::rpns(xc->tcBase());",
115 "predicate_test": predicateTest },
116 ["IsNonSpeculative", "IsUnverifiable"])
117 header_output += BasicDeclare.subst(rpnsIop)
118 decoder_output += BasicConstructor.subst(rpnsIop)
119 exec_output += PredOpExecute.subst(rpnsIop)
120
121 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
122 { "code": "PseudoInst::wakeCPU(xc->tcBase(), R0);",
123 "predicate_test": predicateTest },
124 ["IsNonSpeculative", "IsUnverifiable"])
125 header_output += BasicDeclare.subst(wakeCPUIop)
126 decoder_output += BasicConstructor.subst(wakeCPUIop)
127 exec_output += PredOpExecute.subst(wakeCPUIop)
128
129 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp",
130 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''',
131 "predicate_test": predicateTest })
132 header_output += BasicDeclare.subst(deprecated_ivlbIop)
133 decoder_output += BasicConstructor.subst(deprecated_ivlbIop)
134 exec_output += PredOpExecute.subst(deprecated_ivlbIop)
135
136 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp",
137 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''',
138 "predicate_test": predicateTest })
139 header_output += BasicDeclare.subst(deprecated_ivleIop)
140 decoder_output += BasicConstructor.subst(deprecated_ivleIop)
141 exec_output += PredOpExecute.subst(deprecated_ivleIop)
142
143 deprecated_exit_code = '''
144 warn_once("Obsolete M5 exit instruction encountered.\\n");
145 PseudoInst::m5exit(xc->tcBase(), 0);
146 '''
147
148 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp",
149 { "code": deprecated_exit_code,
150 "predicate_test": predicateTest },
151 ["No_OpClass", "IsNonSpeculative"])
152 header_output += BasicDeclare.subst(deprecated_exitIop)
153 decoder_output += BasicConstructor.subst(deprecated_exitIop)
154 exec_output += PredOpExecute.subst(deprecated_exitIop)
155
156 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
157 { "code": "PseudoInst::m5exit(xc->tcBase(), R0)",
158 "predicate_test": predicateTest },
159 ["No_OpClass", "IsNonSpeculative"])
160 header_output += BasicDeclare.subst(m5exitIop)
161 decoder_output += BasicConstructor.subst(m5exitIop)
162 exec_output += PredOpExecute.subst(m5exitIop)
163
164 loadsymbolCode = '''
165#if FULL_SYSTEM
166 PseudoInst::loadsymbol(xc->tcBase());
167#endif
168 '''
169
170 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
171 { "code": loadsymbolCode,
172 "predicate_test": predicateTest },
173 ["No_OpClass", "IsNonSpeculative"])
174 header_output += BasicDeclare.subst(loadsymbolIop)
175 decoder_output += BasicConstructor.subst(loadsymbolIop)
176 exec_output += PredOpExecute.subst(loadsymbolIop)
177
178 initparamCode = '''
179#if FULL_SYSTEM
180 Rt = xc->tcBase()->getCpuPtr()->system->init_param;
181#endif
182 '''
183
184 initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
185 { "code": initparamCode,
186 "predicate_test": predicateTest })
187 header_output += BasicDeclare.subst(initparamIop)
188 decoder_output += BasicConstructor.subst(initparamIop)
189 exec_output += PredOpExecute.subst(initparamIop)
190
191 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
192 { "code": "PseudoInst::resetstats(xc->tcBase(), R0, R1);",
193 "predicate_test": predicateTest },
194 ["IsNonSpeculative"])
195 header_output += BasicDeclare.subst(resetstatsIop)
196 decoder_output += BasicConstructor.subst(resetstatsIop)
197 exec_output += PredOpExecute.subst(resetstatsIop)
198
199 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
200 { "code": "PseudoInst::dumpstats(xc->tcBase(), R0, R1);",
201 "predicate_test": predicateTest },
202 ["IsNonSpeculative"])
203 header_output += BasicDeclare.subst(dumpstatsIop)
204 decoder_output += BasicConstructor.subst(dumpstatsIop)
205 exec_output += PredOpExecute.subst(dumpstatsIop)
206
207 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
208 { "code": "PseudoInst::dumpresetstats(xc->tcBase(), R0, R1);",
209 "predicate_test": predicateTest },
210 ["IsNonSpeculative"])
211 header_output += BasicDeclare.subst(dumpresetstatsIop)
212 decoder_output += BasicConstructor.subst(dumpresetstatsIop)
213 exec_output += PredOpExecute.subst(dumpresetstatsIop)
214
215 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
216 { "code": "PseudoInst::m5checkpoint(xc->tcBase(), R0, R1);",
217 "predicate_test": predicateTest },
218 ["IsNonSpeculative"])
219 header_output += BasicDeclare.subst(m5checkpointIop)
220 decoder_output += BasicConstructor.subst(m5checkpointIop)
221 exec_output += PredOpExecute.subst(m5checkpointIop)
222
223 m5readfileCode = '''
224#if FULL_SYSTEM
225 R0 = PseudoInst::readfile(xc->tcBase(), R0, R1, R2);
226#endif
227 '''
228 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
229 { "code": m5readfileCode,
230 "predicate_test": predicateTest },
231 ["IsNonSpeculative"])
232 header_output += BasicDeclare.subst(m5readfileIop)
233 decoder_output += BasicConstructor.subst(m5readfileIop)
234 exec_output += PredOpExecute.subst(m5readfileIop)
235
236 m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
237 { "code": "PseudoInst::debugbreak(xc->tcBase());",
238 "predicate_test": predicateTest },
239 ["IsNonSpeculative"])
240 header_output += BasicDeclare.subst(m5breakIop)
241 decoder_output += BasicConstructor.subst(m5breakIop)
242 exec_output += PredOpExecute.subst(m5breakIop)
243
244 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp",
245 { "code": "PseudoInst::switchcpu(xc->tcBase());",
246 "predicate_test": predicateTest },
247 ["IsNonSpeculative"])
248 header_output += BasicDeclare.subst(m5switchcpuIop)
249 decoder_output += BasicConstructor.subst(m5switchcpuIop)
250 exec_output += PredOpExecute.subst(m5switchcpuIop)
251
252 m5addsymbolCode = '''
253#if FULL_SYSTEM
254 PseudoInst::addsymbol(xc->tcBase(), R0, R1);
255#endif
256 '''
257 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
258 { "code": m5addsymbolCode,
259 "predicate_test": predicateTest },
260 ["IsNonSpeculative"])
261 header_output += BasicDeclare.subst(m5addsymbolIop)
262 decoder_output += BasicConstructor.subst(m5addsymbolIop)
263 exec_output += PredOpExecute.subst(m5addsymbolIop)
264
265 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
266 xc->pcState().pc());'''
267 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp",
268 { "code": m5panicCode,
269 "predicate_test": predicateTest },
270 ["IsNonSpeculative"])
271 header_output += BasicDeclare.subst(m5panicIop)
272 decoder_output += BasicConstructor.subst(m5panicIop)
273 exec_output += PredOpExecute.subst(m5panicIop)
274
275}};
| 98
99 quiesceTimeCode = '''
100#if FULL_SYSTEM
101 R0 = PseudoInst::quiesceTime(xc->tcBase());
102#endif
103 '''
104
105 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
106 { "code": quiesceTimeCode,
107 "predicate_test": predicateTest },
108 ["IsNonSpeculative", "IsUnverifiable"])
109 header_output += BasicDeclare.subst(quiesceTimeIop)
110 decoder_output += BasicConstructor.subst(quiesceTimeIop)
111 exec_output += PredOpExecute.subst(quiesceTimeIop)
112
113 rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
114 { "code": "R0 = PseudoInst::rpns(xc->tcBase());",
115 "predicate_test": predicateTest },
116 ["IsNonSpeculative", "IsUnverifiable"])
117 header_output += BasicDeclare.subst(rpnsIop)
118 decoder_output += BasicConstructor.subst(rpnsIop)
119 exec_output += PredOpExecute.subst(rpnsIop)
120
121 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
122 { "code": "PseudoInst::wakeCPU(xc->tcBase(), R0);",
123 "predicate_test": predicateTest },
124 ["IsNonSpeculative", "IsUnverifiable"])
125 header_output += BasicDeclare.subst(wakeCPUIop)
126 decoder_output += BasicConstructor.subst(wakeCPUIop)
127 exec_output += PredOpExecute.subst(wakeCPUIop)
128
129 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp",
130 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''',
131 "predicate_test": predicateTest })
132 header_output += BasicDeclare.subst(deprecated_ivlbIop)
133 decoder_output += BasicConstructor.subst(deprecated_ivlbIop)
134 exec_output += PredOpExecute.subst(deprecated_ivlbIop)
135
136 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp",
137 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''',
138 "predicate_test": predicateTest })
139 header_output += BasicDeclare.subst(deprecated_ivleIop)
140 decoder_output += BasicConstructor.subst(deprecated_ivleIop)
141 exec_output += PredOpExecute.subst(deprecated_ivleIop)
142
143 deprecated_exit_code = '''
144 warn_once("Obsolete M5 exit instruction encountered.\\n");
145 PseudoInst::m5exit(xc->tcBase(), 0);
146 '''
147
148 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp",
149 { "code": deprecated_exit_code,
150 "predicate_test": predicateTest },
151 ["No_OpClass", "IsNonSpeculative"])
152 header_output += BasicDeclare.subst(deprecated_exitIop)
153 decoder_output += BasicConstructor.subst(deprecated_exitIop)
154 exec_output += PredOpExecute.subst(deprecated_exitIop)
155
156 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
157 { "code": "PseudoInst::m5exit(xc->tcBase(), R0)",
158 "predicate_test": predicateTest },
159 ["No_OpClass", "IsNonSpeculative"])
160 header_output += BasicDeclare.subst(m5exitIop)
161 decoder_output += BasicConstructor.subst(m5exitIop)
162 exec_output += PredOpExecute.subst(m5exitIop)
163
164 loadsymbolCode = '''
165#if FULL_SYSTEM
166 PseudoInst::loadsymbol(xc->tcBase());
167#endif
168 '''
169
170 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
171 { "code": loadsymbolCode,
172 "predicate_test": predicateTest },
173 ["No_OpClass", "IsNonSpeculative"])
174 header_output += BasicDeclare.subst(loadsymbolIop)
175 decoder_output += BasicConstructor.subst(loadsymbolIop)
176 exec_output += PredOpExecute.subst(loadsymbolIop)
177
178 initparamCode = '''
179#if FULL_SYSTEM
180 Rt = xc->tcBase()->getCpuPtr()->system->init_param;
181#endif
182 '''
183
184 initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
185 { "code": initparamCode,
186 "predicate_test": predicateTest })
187 header_output += BasicDeclare.subst(initparamIop)
188 decoder_output += BasicConstructor.subst(initparamIop)
189 exec_output += PredOpExecute.subst(initparamIop)
190
191 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
192 { "code": "PseudoInst::resetstats(xc->tcBase(), R0, R1);",
193 "predicate_test": predicateTest },
194 ["IsNonSpeculative"])
195 header_output += BasicDeclare.subst(resetstatsIop)
196 decoder_output += BasicConstructor.subst(resetstatsIop)
197 exec_output += PredOpExecute.subst(resetstatsIop)
198
199 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
200 { "code": "PseudoInst::dumpstats(xc->tcBase(), R0, R1);",
201 "predicate_test": predicateTest },
202 ["IsNonSpeculative"])
203 header_output += BasicDeclare.subst(dumpstatsIop)
204 decoder_output += BasicConstructor.subst(dumpstatsIop)
205 exec_output += PredOpExecute.subst(dumpstatsIop)
206
207 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
208 { "code": "PseudoInst::dumpresetstats(xc->tcBase(), R0, R1);",
209 "predicate_test": predicateTest },
210 ["IsNonSpeculative"])
211 header_output += BasicDeclare.subst(dumpresetstatsIop)
212 decoder_output += BasicConstructor.subst(dumpresetstatsIop)
213 exec_output += PredOpExecute.subst(dumpresetstatsIop)
214
215 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
216 { "code": "PseudoInst::m5checkpoint(xc->tcBase(), R0, R1);",
217 "predicate_test": predicateTest },
218 ["IsNonSpeculative"])
219 header_output += BasicDeclare.subst(m5checkpointIop)
220 decoder_output += BasicConstructor.subst(m5checkpointIop)
221 exec_output += PredOpExecute.subst(m5checkpointIop)
222
223 m5readfileCode = '''
224#if FULL_SYSTEM
225 R0 = PseudoInst::readfile(xc->tcBase(), R0, R1, R2);
226#endif
227 '''
228 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
229 { "code": m5readfileCode,
230 "predicate_test": predicateTest },
231 ["IsNonSpeculative"])
232 header_output += BasicDeclare.subst(m5readfileIop)
233 decoder_output += BasicConstructor.subst(m5readfileIop)
234 exec_output += PredOpExecute.subst(m5readfileIop)
235
236 m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
237 { "code": "PseudoInst::debugbreak(xc->tcBase());",
238 "predicate_test": predicateTest },
239 ["IsNonSpeculative"])
240 header_output += BasicDeclare.subst(m5breakIop)
241 decoder_output += BasicConstructor.subst(m5breakIop)
242 exec_output += PredOpExecute.subst(m5breakIop)
243
244 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp",
245 { "code": "PseudoInst::switchcpu(xc->tcBase());",
246 "predicate_test": predicateTest },
247 ["IsNonSpeculative"])
248 header_output += BasicDeclare.subst(m5switchcpuIop)
249 decoder_output += BasicConstructor.subst(m5switchcpuIop)
250 exec_output += PredOpExecute.subst(m5switchcpuIop)
251
252 m5addsymbolCode = '''
253#if FULL_SYSTEM
254 PseudoInst::addsymbol(xc->tcBase(), R0, R1);
255#endif
256 '''
257 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
258 { "code": m5addsymbolCode,
259 "predicate_test": predicateTest },
260 ["IsNonSpeculative"])
261 header_output += BasicDeclare.subst(m5addsymbolIop)
262 decoder_output += BasicConstructor.subst(m5addsymbolIop)
263 exec_output += PredOpExecute.subst(m5addsymbolIop)
264
265 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
266 xc->pcState().pc());'''
267 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp",
268 { "code": m5panicCode,
269 "predicate_test": predicateTest },
270 ["IsNonSpeculative"])
271 header_output += BasicDeclare.subst(m5panicIop)
272 decoder_output += BasicConstructor.subst(m5panicIop)
273 exec_output += PredOpExecute.subst(m5panicIop)
274
275}};
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