1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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185 { "code": loadsymbolCode,
186 "predicate_test": predicateTest },
187 ["No_OpClass", "IsNonSpeculative"])
188 header_output += BasicDeclare.subst(loadsymbolIop)
189 decoder_output += BasicConstructor.subst(loadsymbolIop)
190 exec_output += PredOpExecute.subst(loadsymbolIop)
191
192 initparamCode = '''
193 Rt = PseudoInst::initParam(xc->tcBase());
194 '''
195
196 initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
197 { "code": initparamCode,
198 "predicate_test": predicateTest })
199 header_output += BasicDeclare.subst(initparamIop)
200 decoder_output += BasicConstructor.subst(initparamIop)
201 exec_output += PredOpExecute.subst(initparamIop)
202
203 resetstats_code = '''
204 PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
205 '''
206

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