1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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49 }
50 '''
51 exec_output = '''
52 uint64_t join32to64(uint32_t r1, uint32_t r0);
53 '''
54
55
56 armCode = '''
57 PseudoInst::arm(xc->tcBase());
58 '''
59 armIop = InstObjParams("arm", "Arm", "PredOp",
60 { "code": armCode,
61 "predicate_test": predicateTest },
62 ["IsNonSpeculative"])
63 header_output += BasicDeclare.subst(armIop)
64 decoder_output += BasicConstructor.subst(armIop)
65 exec_output += PredOpExecute.subst(armIop)
66
67 quiesceCode = '''
68 PseudoInst::quiesce(xc->tcBase());
69 '''
70 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
71 { "code": quiesceCode,
72 "predicate_test": predicateTest },
73 ["IsNonSpeculative", "IsQuiesce"])
74 header_output += BasicDeclare.subst(quiesceIop)
75 decoder_output += BasicConstructor.subst(quiesceIop)
76 exec_output += QuiescePredOpExecute.subst(quiesceIop)
77
78 quiesceNsCode = '''
79 PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
80 '''
81
82 quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
83 { "code": quiesceNsCode,
84 "predicate_test": predicateTest },
85 ["IsNonSpeculative", "IsQuiesce"])
86 header_output += BasicDeclare.subst(quiesceNsIop)
87 decoder_output += BasicConstructor.subst(quiesceNsIop)
88 exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
89
90 quiesceCyclesCode = '''
91 PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
92 '''
93
94 quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
95 { "code": quiesceCyclesCode,
96 "predicate_test": predicateTest },
97 ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
98 header_output += BasicDeclare.subst(quiesceCyclesIop)
99 decoder_output += BasicConstructor.subst(quiesceCyclesIop)
100 exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
101
102 quiesceTimeCode = '''
103 uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
104 R0 = bits(qt_val, 31, 0);
105 R1 = bits(qt_val, 63, 32);
106 '''
107
108 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
109 { "code": quiesceTimeCode,
110 "predicate_test": predicateTest },
111 ["IsNonSpeculative", "IsUnverifiable"])
112 header_output += BasicDeclare.subst(quiesceTimeIop)
113 decoder_output += BasicConstructor.subst(quiesceTimeIop)

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173 { "code": m5exit_code,
174 "predicate_test": predicateTest },
175 ["No_OpClass", "IsNonSpeculative"])
176 header_output += BasicDeclare.subst(m5exitIop)
177 decoder_output += BasicConstructor.subst(m5exitIop)
178 exec_output += PredOpExecute.subst(m5exitIop)
179
180 loadsymbolCode = '''
181 PseudoInst::loadsymbol(xc->tcBase());
182 '''
183
184 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
185 { "code": loadsymbolCode,
186 "predicate_test": predicateTest },
187 ["No_OpClass", "IsNonSpeculative"])
188 header_output += BasicDeclare.subst(loadsymbolIop)
189 decoder_output += BasicConstructor.subst(loadsymbolIop)
190 exec_output += PredOpExecute.subst(loadsymbolIop)
191
192 initparamCode = '''
193#if FULL_SYSTEM
194 Rt = PseudoInst::initParam(xc->tcBase());
195#else
196 PseudoInst::panicFsOnlyPseudoInst("initparam");
197 Rt = 0;
198#endif
199 '''
200
201 initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
202 { "code": initparamCode,
203 "predicate_test": predicateTest })
204 header_output += BasicDeclare.subst(initparamIop)
205 decoder_output += BasicConstructor.subst(initparamIop)

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246 { "code": m5checkpoint_code,
247 "predicate_test": predicateTest },
248 ["IsNonSpeculative"])
249 header_output += BasicDeclare.subst(m5checkpointIop)
250 decoder_output += BasicConstructor.subst(m5checkpointIop)
251 exec_output += PredOpExecute.subst(m5checkpointIop)
252
253 m5readfileCode = '''
254 int n = 4;
255 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
256 R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
257 '''
258 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
259 { "code": m5readfileCode,
260 "predicate_test": predicateTest },
261 ["IsNonSpeculative"])
262 header_output += BasicDeclare.subst(m5readfileIop)
263 decoder_output += BasicConstructor.subst(m5readfileIop)
264 exec_output += PredOpExecute.subst(m5readfileIop)

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275 { "code": "PseudoInst::switchcpu(xc->tcBase());",
276 "predicate_test": predicateTest },
277 ["IsNonSpeculative"])
278 header_output += BasicDeclare.subst(m5switchcpuIop)
279 decoder_output += BasicConstructor.subst(m5switchcpuIop)
280 exec_output += PredOpExecute.subst(m5switchcpuIop)
281
282 m5addsymbolCode = '''
283 PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
284 '''
285 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
286 { "code": m5addsymbolCode,
287 "predicate_test": predicateTest },
288 ["IsNonSpeculative"])
289 header_output += BasicDeclare.subst(m5addsymbolIop)
290 decoder_output += BasicConstructor.subst(m5addsymbolIop)
291 exec_output += PredOpExecute.subst(m5addsymbolIop)

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