data64.isa (14241:cef003034ff2) data64.isa (14242:076b215de8d4)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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326 mnemonic);
327 }
328
329 fault = this->trap(xc->tcBase(), flat_idx, el, imm);
330 if (fault != NoFault) return fault;
331 '''
332
333 msr_check_code = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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326 mnemonic);
327 }
328
329 fault = this->trap(xc->tcBase(), flat_idx, el, imm);
330 if (fault != NoFault) return fault;
331 '''
332
333 msr_check_code = '''
334 auto pre_flat = (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase());
334 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
335 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
335 flattenRegId(RegId(MiscRegClass, dest)).index();
336 flattenRegId(RegId(MiscRegClass, pre_flat)).index();
336 CPSR cpsr = Cpsr;
337 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
338 %s
339 ''' % (msrMrs64EnabledCheckCode % ('Write'),)
340
341 mrs_check_code = '''
337 CPSR cpsr = Cpsr;
338 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
339 %s
340 ''' % (msrMrs64EnabledCheckCode % ('Write'),)
341
342 mrs_check_code = '''
343 auto pre_flat = (MiscRegIndex)snsBankedIndex64(op1, xc->tcBase());
342 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
344 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
343 flattenRegId(RegId(MiscRegClass, op1)).index();
345 flattenRegId(RegId(MiscRegClass, pre_flat)).index();
344 CPSR cpsr = Cpsr;
345 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
346 %s
347 ''' % (msrMrs64EnabledCheckCode % ('Read'),)
348
349
350 mrsCode = mrs_check_code + '''
351 XDest = MiscOp1_ud;

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504 decoder_output += DCStore64Constructor.subst(msrDCIVACIop);
505 exec_output += DCStore64Execute.subst(msrDCIVACIop);
506 exec_output += DCStore64InitiateAcc.subst(msrDCIVACIop);
507 exec_output += Store64CompleteAcc.subst(msrDCIVACIop);
508
509 def buildMsrImmInst(mnem, inst_name, code):
510 global header_output, decoder_output, exec_output
511 msrImmPermission = '''
346 CPSR cpsr = Cpsr;
347 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
348 %s
349 ''' % (msrMrs64EnabledCheckCode % ('Read'),)
350
351
352 mrsCode = mrs_check_code + '''
353 XDest = MiscOp1_ud;

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506 decoder_output += DCStore64Constructor.subst(msrDCIVACIop);
507 exec_output += DCStore64Execute.subst(msrDCIVACIop);
508 exec_output += DCStore64InitiateAcc.subst(msrDCIVACIop);
509 exec_output += Store64CompleteAcc.subst(msrDCIVACIop);
510
511 def buildMsrImmInst(mnem, inst_name, code):
512 global header_output, decoder_output, exec_output
513 msrImmPermission = '''
512 auto misc_index = (MiscRegIndex) xc->tcBase()->flattenRegId(
513 RegId(MiscRegClass, dest)).index();
514 auto pre_flat =
515 (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase());
516 MiscRegIndex misc_index = (MiscRegIndex) xc->tcBase()->
517 flattenRegId(RegId(MiscRegClass, pre_flat)).index();
514
515 if (!miscRegInfo[misc_index][MISCREG_IMPLEMENTED]) {
516 return std::make_shared<UndefinedInstruction>(
517 machInst, false,
518 mnemonic);
519 }
520
521 if (!canWriteAArch64SysReg(misc_index,

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519 if (!miscRegInfo[misc_index][MISCREG_IMPLEMENTED]) {
520 return std::make_shared<UndefinedInstruction>(
521 machInst, false,
522 mnemonic);
523 }
524
525 if (!canWriteAArch64SysReg(misc_index,

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