data64.isa (13363:15eae7ca2bfd) data64.isa (13364:055bf0fa0f02)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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321 )
322 return std::make_shared<UndefinedInstruction>(
323 machInst, 0, EC_TRAPPED_MSR_MRS_64,
324 mnemonic);
325 return std::make_shared<UndefinedInstruction>(machInst, false,
326 mnemonic);
327 }
328
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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321 )
322 return std::make_shared<UndefinedInstruction>(
323 machInst, 0, EC_TRAPPED_MSR_MRS_64,
324 mnemonic);
325 return std::make_shared<UndefinedInstruction>(machInst, false,
326 mnemonic);
327 }
328
329 // Check for traps to supervisor (FP/SIMD regs)
330 if (el <= EL1 && msrMrs64TrapToSup(flat_idx, el, Cpacr64))
331 return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
332 EC_TRAPPED_SIMD_FP);
333
334 bool is_vfp_neon = false;
335
336 // Check for traps to hypervisor
337 if ((ArmSystem::haveVirtualization(xc->tcBase()) && el <= EL2) &&
338 msrMrs64TrapToHyp(flat_idx, el, %s, CptrEl264, Hcr64,
339 Scr64, cpsr, &is_vfp_neon)) {
340
341 return std::make_shared<HypervisorTrap>(
342 machInst, is_vfp_neon ? 0x1E00000 : imm,
343 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
344 }
345
346 // Check for traps to secure monitor
347 if ((ArmSystem::haveSecurity(xc->tcBase()) && el <= EL3) &&
348 msrMrs64TrapToMon(flat_idx, CptrEl364, el, &is_vfp_neon)) {
349 return std::make_shared<SecureMonitorTrap>(
350 machInst,
351 is_vfp_neon ? 0x1E00000 : imm,
352 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
353 }
329 fault = this->trap(xc->tcBase(), flat_idx, el, imm);
330 if (fault != NoFault) return fault;
354 '''
355
356 mrsCode = '''
357 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
358 flattenRegId(RegId(MiscRegClass, op1)).index();
359 CPSR cpsr = Cpsr;
360 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
361 %s
362 XDest = MiscOp1_ud;
331 '''
332
333 mrsCode = '''
334 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
335 flattenRegId(RegId(MiscRegClass, op1)).index();
336 CPSR cpsr = Cpsr;
337 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
338 %s
339 XDest = MiscOp1_ud;
363 ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),)
340 ''' % (msrMrs64EnabledCheckCode % ('Read'),)
364
365 mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
366 mrsCode,
367 ["IsSerializeBefore"])
368 header_output += RegMiscRegOp64Declare.subst(mrsIop)
369 decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
370 exec_output += BasicExecute.subst(mrsIop)
371

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379
380 msrCode = '''
381 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
382 flattenRegId(RegId(MiscRegClass, dest)).index();
383 CPSR cpsr = Cpsr;
384 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
385 %s
386 MiscDest_ud = XOp1;
341
342 mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
343 mrsCode,
344 ["IsSerializeBefore"])
345 header_output += RegMiscRegOp64Declare.subst(mrsIop)
346 decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
347 exec_output += BasicExecute.subst(mrsIop)
348

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356
357 msrCode = '''
358 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
359 flattenRegId(RegId(MiscRegClass, dest)).index();
360 CPSR cpsr = Cpsr;
361 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
362 %s
363 MiscDest_ud = XOp1;
387 ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),)
364 ''' % (msrMrs64EnabledCheckCode % ('Write'),)
388
389 msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
390 msrCode,
391 ["IsSerializeAfter", "IsNonSpeculative"])
392 header_output += MiscRegRegOp64Declare.subst(msrIop)
393 decoder_output += MiscRegRegOp64Constructor.subst(msrIop)
394 exec_output += BasicExecute.subst(msrIop)
395

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402 ''')
403
404 msr_check_code = '''
405 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
406 flattenRegId(RegId(MiscRegClass, dest)).index();
407 CPSR cpsr = Cpsr;
408 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
409 %s
365
366 msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
367 msrCode,
368 ["IsSerializeAfter", "IsNonSpeculative"])
369 header_output += MiscRegRegOp64Declare.subst(msrIop)
370 decoder_output += MiscRegRegOp64Constructor.subst(msrIop)
371 exec_output += BasicExecute.subst(msrIop)
372

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379 ''')
380
381 msr_check_code = '''
382 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
383 flattenRegId(RegId(MiscRegClass, dest)).index();
384 CPSR cpsr = Cpsr;
385 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
386 %s
410 ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),)
387 ''' % (msrMrs64EnabledCheckCode % ('Write'),)
411
412
413 msrdczva_ea_code = msr_check_code
414 msrdczva_ea_code += '''
415 Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO |
416 ArmISA::TLB::MustBeOne;
417 EA = XBase;
418 assert(!(Dczid & 0x10));

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389
390 msrdczva_ea_code = msr_check_code
391 msrdczva_ea_code += '''
392 Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO |
393 ArmISA::TLB::MustBeOne;
394 EA = XBase;
395 assert(!(Dczid & 0x10));

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