data64.isa (12280:a44a2326a02b) data64.isa (12359:8fb4630c444f)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016 ARM Limited
3// Copyright (c) 2011-2013, 2016-2017 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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312 ''')
313
314 msrMrs64EnabledCheckCode = '''
315 // Check for read/write access right
316 if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) {
317 if (flat_idx == MISCREG_DAIF ||
318 flat_idx == MISCREG_DC_ZVA_Xt ||
319 flat_idx == MISCREG_DC_CVAC_Xt ||
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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312 ''')
313
314 msrMrs64EnabledCheckCode = '''
315 // Check for read/write access right
316 if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) {
317 if (flat_idx == MISCREG_DAIF ||
318 flat_idx == MISCREG_DC_ZVA_Xt ||
319 flat_idx == MISCREG_DC_CVAC_Xt ||
320 flat_idx == MISCREG_DC_CIVAC_Xt
320 flat_idx == MISCREG_DC_CIVAC_Xt ||
321 flat_idx == MISCREG_DC_IVAC_Xt
321 )
322 return std::make_shared<UndefinedInstruction>(
323 machInst, 0, EC_TRAPPED_MSR_MRS_64,
324 mnemonic);
325 return std::make_shared<UndefinedInstruction>(machInst, false,
326 mnemonic);
327 }
328

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422 "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
423 header_output += DCStore64Declare.subst(msrDCZVAIop);
424 decoder_output += DCStore64Constructor.subst(msrDCZVAIop);
425 exec_output += DCStore64Execute.subst(msrDCZVAIop);
426 exec_output += DCStore64InitiateAcc.subst(msrDCZVAIop);
427 exec_output += Store64CompleteAcc.subst(msrDCZVAIop);
428
429
322 )
323 return std::make_shared<UndefinedInstruction>(
324 machInst, 0, EC_TRAPPED_MSR_MRS_64,
325 mnemonic);
326 return std::make_shared<UndefinedInstruction>(machInst, false,
327 mnemonic);
328 }
329

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423 "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
424 header_output += DCStore64Declare.subst(msrDCZVAIop);
425 decoder_output += DCStore64Constructor.subst(msrDCZVAIop);
426 exec_output += DCStore64Execute.subst(msrDCZVAIop);
427 exec_output += DCStore64InitiateAcc.subst(msrDCZVAIop);
428 exec_output += Store64CompleteAcc.subst(msrDCZVAIop);
429
430
431 msrdccvau_ea_code = '''
432 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId(
433 RegId(MiscRegClass, dest)).index();
434 CPSR cpsr = Cpsr;
435 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
436 '''
430
437
438 msrdccvau_ea_code += msrMrs64EnabledCheckCode % ('Write', 'false')
439 msrdccvau_ea_code += '''
440 Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POU |
441 ArmISA::TLB::MustBeOne;
442 EA = XBase;
443 System *sys = xc->tcBase()->getSystemPtr();
444 Addr op_size = sys->cacheLineSize();
445 EA &= ~(op_size - 1);
446 '''
447
448 msrDCCVAUIop = InstObjParams("dc cvau", "Dccvau", "SysDC64",
449 { "ea_code" : msrdccvau_ea_code,
450 "memacc_code" : ";", "use_uops" : 0,
451 "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
452 header_output += DCStore64Declare.subst(msrDCCVAUIop);
453 decoder_output += DCStore64Constructor.subst(msrDCCVAUIop);
454 exec_output += DCStore64Execute.subst(msrDCCVAUIop);
455 exec_output += DCStore64InitiateAcc.subst(msrDCCVAUIop);
456 exec_output += Store64CompleteAcc.subst(msrDCCVAUIop);
457
458
459 msrdccvac_ea_code = '''
460 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId(
461 RegId(MiscRegClass, dest)).index();
462 CPSR cpsr = Cpsr;
463 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
464 '''
465
466 msrdccvac_ea_code += msrMrs64EnabledCheckCode % ('Write', 'false')
467 msrdccvac_ea_code += '''
468 Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POC |
469 ArmISA::TLB::MustBeOne;
470 EA = XBase;
471 System *sys = xc->tcBase()->getSystemPtr();
472 Addr op_size = sys->cacheLineSize();
473 EA &= ~(op_size - 1);
474 '''
475
476 msrDCCVACIop = InstObjParams("dc cvac", "Dccvac", "SysDC64",
477 { "ea_code" : msrdccvac_ea_code,
478 "memacc_code" : ";", "use_uops" : 0,
479 "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
480 header_output += DCStore64Declare.subst(msrDCCVACIop);
481 decoder_output += DCStore64Constructor.subst(msrDCCVACIop);
482 exec_output += DCStore64Execute.subst(msrDCCVACIop);
483 exec_output += DCStore64InitiateAcc.subst(msrDCCVACIop);
484 exec_output += Store64CompleteAcc.subst(msrDCCVACIop);
485
486
487 msrdccivac_ea_code = '''
488 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId(
489 RegId(MiscRegClass, dest)).index();
490 CPSR cpsr = Cpsr;
491 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
492 '''
493
494 msrdccivac_ea_code += msrMrs64EnabledCheckCode % ('Write', 'false')
495 msrdccivac_ea_code += '''
496 Request::Flags memAccessFlags = Request::CLEAN |
497 Request::INVALIDATE | Request::DST_POC | ArmISA::TLB::MustBeOne;
498 EA = XBase;
499 System *sys = xc->tcBase()->getSystemPtr();
500 Addr op_size = sys->cacheLineSize();
501 EA &= ~(op_size - 1);
502 '''
503
504 msrDCCIVACIop = InstObjParams("dc civac", "Dccivac", "SysDC64",
505 { "ea_code" : msrdccivac_ea_code,
506 "memacc_code" : ";", "use_uops" : 0,
507 "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
508 header_output += DCStore64Declare.subst(msrDCCIVACIop);
509 decoder_output += DCStore64Constructor.subst(msrDCCIVACIop);
510 exec_output += DCStore64Execute.subst(msrDCCIVACIop);
511 exec_output += DCStore64InitiateAcc.subst(msrDCCIVACIop);
512 exec_output += Store64CompleteAcc.subst(msrDCCIVACIop);
513
514
515 msrdcivac_ea_code = '''
516 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId(
517 RegId(MiscRegClass, dest)).index();
518 CPSR cpsr = Cpsr;
519 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
520 '''
521
522 msrdcivac_ea_code += msrMrs64EnabledCheckCode % ('Write', 'false')
523 msrdcivac_ea_code += '''
524 Request::Flags memAccessFlags = Request::INVALIDATE |
525 Request::DST_POC | ArmISA::TLB::MustBeOne;
526 EA = XBase;
527 System *sys = xc->tcBase()->getSystemPtr();
528 Addr op_size = sys->cacheLineSize();
529 EA &= ~(op_size - 1);
530 '''
531
532 msrDCIVACIop = InstObjParams("dc ivac", "Dcivac", "SysDC64",
533 { "ea_code" : msrdcivac_ea_code,
534 "memacc_code" : ";", "use_uops" : 0,
535 "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
536 header_output += DCStore64Declare.subst(msrDCIVACIop);
537 decoder_output += DCStore64Constructor.subst(msrDCIVACIop);
538 exec_output += DCStore64Execute.subst(msrDCIVACIop);
539 exec_output += DCStore64InitiateAcc.subst(msrDCIVACIop);
540 exec_output += Store64CompleteAcc.subst(msrDCIVACIop);
541
542
431 buildDataXImmInst("msrSP", '''
432 if (!canWriteAArch64SysReg(
433 (MiscRegIndex) xc->tcBase()->flattenRegId(
434 RegId(MiscRegClass, dest)).index(),
435 Scr64, Cpsr, xc->tcBase())) {
436 return std::make_shared<UndefinedInstruction>(machInst, false,
437 mnemonic);
438 }

--- 80 unchanged lines hidden --- 		543 buildDataXImmInst("msrSP", '''
544 if (!canWriteAArch64SysReg(
545 (MiscRegIndex) xc->tcBase()->flattenRegId(
546 RegId(MiscRegClass, dest)).index(),
547 Scr64, Cpsr, xc->tcBase())) {
548 return std::make_shared<UndefinedInstruction>(machInst, false,
549 mnemonic);
550 }

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