data64.isa (12258:08990d24fe41) data64.isa (12280:a44a2326a02b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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346 msrMrs64TrapToMon(flat_idx, CptrEl364, el, &is_vfp_neon)) {
347 return std::make_shared<SecureMonitorTrap>(
348 machInst,
349 is_vfp_neon ? 0x1E00000 : imm,
350 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
351 }
352 '''
353
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 337 unchanged lines hidden (view full) ---

346 msrMrs64TrapToMon(flat_idx, CptrEl364, el, &is_vfp_neon)) {
347 return std::make_shared<SecureMonitorTrap>(
348 machInst,
349 is_vfp_neon ? 0x1E00000 : imm,
350 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
351 }
352 '''
353
354 buildDataXImmInst("mrs", '''
354 mrsCode = '''
355 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
356 flattenRegId(RegId(MiscRegClass, op1)).index();
357 CPSR cpsr = Cpsr;
358 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
359 %s
360 XDest = MiscOp1_ud;
355 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
356 flattenRegId(RegId(MiscRegClass, op1)).index();
357 CPSR cpsr = Cpsr;
358 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
359 %s
360 XDest = MiscOp1_ud;
361 ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),),
362 ["IsSerializeBefore"])
361 ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),)
363
362
363 mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
364 mrsCode,
365 ["IsSerializeBefore"])
366 header_output += RegMiscRegOp64Declare.subst(mrsIop)
367 decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
368 exec_output += BasicExecute.subst(mrsIop)
369
364 buildDataXRegInst("mrsNZCV", 1, '''
365 CPSR cpsr = 0;
366 cpsr.nz = CondCodesNZ;
367 cpsr.c = CondCodesC;
368 cpsr.v = CondCodesV;
369 XDest = cpsr;
370 ''')
371
370 buildDataXRegInst("mrsNZCV", 1, '''
371 CPSR cpsr = 0;
372 cpsr.nz = CondCodesNZ;
373 cpsr.c = CondCodesC;
374 cpsr.v = CondCodesV;
375 XDest = cpsr;
376 ''')
377
372 buildDataXImmInst("msr", '''
378 msrCode = '''
373 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
374 flattenRegId(RegId(MiscRegClass, dest)).index();
375 CPSR cpsr = Cpsr;
376 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
377 %s
378 MiscDest_ud = XOp1;
379 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
380 flattenRegId(RegId(MiscRegClass, dest)).index();
381 CPSR cpsr = Cpsr;
382 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
383 %s
384 MiscDest_ud = XOp1;
379 ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),),
380 ["IsSerializeAfter", "IsNonSpeculative"])
385 ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),)
381
386
387 msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
388 msrCode,
389 ["IsSerializeAfter", "IsNonSpeculative"])
390 header_output += MiscRegRegOp64Declare.subst(msrIop)
391 decoder_output += MiscRegRegOp64Constructor.subst(msrIop)
392 exec_output += BasicExecute.subst(msrIop)
393
394
382 buildDataXRegInst("msrNZCV", 1, '''
383 CPSR cpsr = XOp1;
384 CondCodesNZ = cpsr.nz;
385 CondCodesC = cpsr.c;
386 CondCodesV = cpsr.v;
387 ''')
388
389 msrdczva_ea_code = '''

--- 116 unchanged lines hidden --- 		395 buildDataXRegInst("msrNZCV", 1, '''
396 CPSR cpsr = XOp1;
397 CondCodesNZ = cpsr.nz;
398 CondCodesC = cpsr.c;
399 CondCodesV = cpsr.v;
400 ''')
401
402 msrdczva_ea_code = '''

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