data64.isa (11862:ce333ae9ee02) data64.isa (12106:7784fac1b159)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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323 machInst,
324 is_vfp_neon ? 0x1E00000 : imm,
325 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
326 }
327 '''
328
329 buildDataXImmInst("mrs", '''
330 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 314 unchanged lines hidden (view full) ---

323 machInst,
324 is_vfp_neon ? 0x1E00000 : imm,
325 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
326 }
327 '''
328
329 buildDataXImmInst("mrs", '''
330 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
331 flattenMiscIndex(op1);
331 flattenRegId(RegId(MiscRegClass, op1)).index();
332 CPSR cpsr = Cpsr;
333 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
334 %s
335 XDest = MiscOp1_ud;
336 ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),),
337 ["IsSerializeBefore"])
338
339 buildDataXRegInst("mrsNZCV", 1, '''
340 CPSR cpsr = 0;
341 cpsr.nz = CondCodesNZ;
342 cpsr.c = CondCodesC;
343 cpsr.v = CondCodesV;
344 XDest = cpsr;
345 ''')
346
347 buildDataXImmInst("msr", '''
348 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
332 CPSR cpsr = Cpsr;
333 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
334 %s
335 XDest = MiscOp1_ud;
336 ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),),
337 ["IsSerializeBefore"])
338
339 buildDataXRegInst("mrsNZCV", 1, '''
340 CPSR cpsr = 0;
341 cpsr.nz = CondCodesNZ;
342 cpsr.c = CondCodesC;
343 cpsr.v = CondCodesV;
344 XDest = cpsr;
345 ''')
346
347 buildDataXImmInst("msr", '''
348 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
349 flattenMiscIndex(dest);
349 flattenRegId(RegId(MiscRegClass, dest)).index();
350 CPSR cpsr = Cpsr;
351 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
352 %s
353 MiscDest_ud = XOp1;
354 ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),),
355 ["IsSerializeAfter", "IsNonSpeculative"])
356
357 buildDataXRegInst("msrNZCV", 1, '''
358 CPSR cpsr = XOp1;
359 CondCodesNZ = cpsr.nz;
360 CondCodesC = cpsr.c;
361 CondCodesV = cpsr.v;
362 ''')
363
364 msrdczva_ea_code = '''
350 CPSR cpsr = Cpsr;
351 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
352 %s
353 MiscDest_ud = XOp1;
354 ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),),
355 ["IsSerializeAfter", "IsNonSpeculative"])
356
357 buildDataXRegInst("msrNZCV", 1, '''
358 CPSR cpsr = XOp1;
359 CondCodesNZ = cpsr.nz;
360 CondCodesC = cpsr.c;
361 CondCodesV = cpsr.v;
362 ''')
363
364 msrdczva_ea_code = '''
365 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
365 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId(
366 RegId(MiscRegClass, dest)).index();
366 CPSR cpsr = Cpsr;
367 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
368 '''
369
370 msrdczva_ea_code += msrMrs64EnabledCheckCode % ('Write', 'false')
371 msrdczva_ea_code += '''
372 Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO|ArmISA::TLB::MustBeOne;
373 EA = XBase;

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386 exec_output += DCStore64Execute.subst(msrDCZVAIop);
387 exec_output += DCStore64InitiateAcc.subst(msrDCZVAIop);
388 exec_output += Store64CompleteAcc.subst(msrDCZVAIop);
389
390
391
392 buildDataXImmInst("msrSP", '''
393 if (!canWriteAArch64SysReg(
367 CPSR cpsr = Cpsr;
368 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
369 '''
370
371 msrdczva_ea_code += msrMrs64EnabledCheckCode % ('Write', 'false')
372 msrdczva_ea_code += '''
373 Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO|ArmISA::TLB::MustBeOne;
374 EA = XBase;

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387 exec_output += DCStore64Execute.subst(msrDCZVAIop);
388 exec_output += DCStore64InitiateAcc.subst(msrDCZVAIop);
389 exec_output += Store64CompleteAcc.subst(msrDCZVAIop);
390
391
392
393 buildDataXImmInst("msrSP", '''
394 if (!canWriteAArch64SysReg(
394 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
395 (MiscRegIndex) xc->tcBase()->flattenRegId(
396 RegId(MiscRegClass, dest)).index(),
395 Scr64, Cpsr, xc->tcBase())) {
396 return std::make_shared<UndefinedInstruction>(machInst, false,
397 mnemonic);
398 }
399 MiscDest_ud = imm;
400 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
401
402 buildDataXImmInst("msrDAIFSet", '''
403 if (!canWriteAArch64SysReg(
397 Scr64, Cpsr, xc->tcBase())) {
398 return std::make_shared<UndefinedInstruction>(machInst, false,
399 mnemonic);
400 }
401 MiscDest_ud = imm;
402 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
403
404 buildDataXImmInst("msrDAIFSet", '''
405 if (!canWriteAArch64SysReg(
404 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
406 (MiscRegIndex) xc->tcBase()->flattenRegId(
407 RegId(MiscRegClass, dest)).index(),
405 Scr64, Cpsr, xc->tcBase())) {
406 return std::make_shared<UndefinedInstruction>(
407 machInst, 0, EC_TRAPPED_MSR_MRS_64,
408 mnemonic);
409 }
410 CPSR cpsr = Cpsr;
411 cpsr.daif = cpsr.daif | imm;
412 Cpsr = cpsr;
413 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
414
415 buildDataXImmInst("msrDAIFClr", '''
416 if (!canWriteAArch64SysReg(
408 Scr64, Cpsr, xc->tcBase())) {
409 return std::make_shared<UndefinedInstruction>(
410 machInst, 0, EC_TRAPPED_MSR_MRS_64,
411 mnemonic);
412 }
413 CPSR cpsr = Cpsr;
414 cpsr.daif = cpsr.daif | imm;
415 Cpsr = cpsr;
416 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
417
418 buildDataXImmInst("msrDAIFClr", '''
419 if (!canWriteAArch64SysReg(
417 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
420 (MiscRegIndex) xc->tcBase()->flattenRegId(
421 RegId(MiscRegClass, dest)).index(),
418 Scr64, Cpsr, xc->tcBase())) {
419 return std::make_shared<UndefinedInstruction>(
420 machInst, 0, EC_TRAPPED_MSR_MRS_64,
421 mnemonic);
422 }
423 CPSR cpsr = Cpsr;
424 cpsr.daif = cpsr.daif & ~imm;
425 Cpsr = cpsr;

--- 51 unchanged lines hidden --- 		422 Scr64, Cpsr, xc->tcBase())) {
423 return std::make_shared<UndefinedInstruction>(
424 machInst, 0, EC_TRAPPED_MSR_MRS_64,
425 mnemonic);
426 }
427 CPSR cpsr = Cpsr;
428 cpsr.daif = cpsr.daif & ~imm;
429 Cpsr = cpsr;

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