data64.isa (10037:5cac77888310) | data64.isa (10205:3ca67d0e0e7e) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2011-2013 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 280 unchanged lines hidden (view full) --- 289 msrMrs64EnabledCheckCode = ''' 290 // Check for read/write access right 291 if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) { 292 if (flat_idx == MISCREG_DAIF || 293 flat_idx == MISCREG_DC_ZVA_Xt || 294 flat_idx == MISCREG_DC_CVAC_Xt || 295 flat_idx == MISCREG_DC_CIVAC_Xt 296 ) | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2011-2013 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 280 unchanged lines hidden (view full) --- 289 msrMrs64EnabledCheckCode = ''' 290 // Check for read/write access right 291 if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) { 292 if (flat_idx == MISCREG_DAIF || 293 flat_idx == MISCREG_DC_ZVA_Xt || 294 flat_idx == MISCREG_DC_CVAC_Xt || 295 flat_idx == MISCREG_DC_CIVAC_Xt 296 ) |
297 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64); | 297 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, 298 mnemonic); |
298 return new UndefinedInstruction(machInst, false, mnemonic); 299 } 300 301 // Check for traps to supervisor (FP/SIMD regs) 302 if (el <= EL1 && msrMrs64TrapToSup(flat_idx, el, Cpacr64)) 303 return new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_SIMD_FP); 304 305 bool is_vfp_neon = false; --- 85 unchanged lines hidden (view full) --- 391 } 392 MiscDest_ud = imm; 393 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"]) 394 395 buildDataXImmInst("msrDAIFSet", ''' 396 if (!canWriteAArch64SysReg( 397 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), 398 Scr64, Cpsr, xc->tcBase())) { | 299 return new UndefinedInstruction(machInst, false, mnemonic); 300 } 301 302 // Check for traps to supervisor (FP/SIMD regs) 303 if (el <= EL1 && msrMrs64TrapToSup(flat_idx, el, Cpacr64)) 304 return new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_SIMD_FP); 305 306 bool is_vfp_neon = false; --- 85 unchanged lines hidden (view full) --- 392 } 393 MiscDest_ud = imm; 394 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"]) 395 396 buildDataXImmInst("msrDAIFSet", ''' 397 if (!canWriteAArch64SysReg( 398 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), 399 Scr64, Cpsr, xc->tcBase())) { |
399 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64); | 400 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, 401 mnemonic); |
400 } 401 CPSR cpsr = Cpsr; 402 cpsr.daif = cpsr.daif | imm; 403 Cpsr = cpsr; 404 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"]) 405 406 buildDataXImmInst("msrDAIFClr", ''' 407 if (!canWriteAArch64SysReg( 408 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), 409 Scr64, Cpsr, xc->tcBase())) { | 402 } 403 CPSR cpsr = Cpsr; 404 cpsr.daif = cpsr.daif | imm; 405 Cpsr = cpsr; 406 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"]) 407 408 buildDataXImmInst("msrDAIFClr", ''' 409 if (!canWriteAArch64SysReg( 410 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), 411 Scr64, Cpsr, xc->tcBase())) { |
410 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64); | 412 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, 413 mnemonic); |
411 } 412 CPSR cpsr = Cpsr; 413 cpsr.daif = cpsr.daif & ~imm; 414 Cpsr = cpsr; 415 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"]) 416 417 def buildDataXCompInst(mnem, instType, suffix, code): 418 global header_output, decoder_output, exec_output --- 47 unchanged lines hidden --- | 414 } 415 CPSR cpsr = Cpsr; 416 cpsr.daif = cpsr.daif & ~imm; 417 Cpsr = cpsr; 418 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"]) 419 420 def buildDataXCompInst(mnem, instType, suffix, code): 421 global header_output, decoder_output, exec_output --- 47 unchanged lines hidden --- |