1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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312 ''')
313
314 msrMrs64EnabledCheckCode = '''
315 // Check for read/write access right
316 if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) {
317 if (flat_idx == MISCREG_DAIF ||
318 flat_idx == MISCREG_DC_ZVA_Xt ||
319 flat_idx == MISCREG_DC_CVAC_Xt ||
320 flat_idx == MISCREG_DC_CIVAC_Xt
321 )
322 return std::make_shared<UndefinedInstruction>(
323 machInst, 0, EC_TRAPPED_MSR_MRS_64,
324 mnemonic);
325 return std::make_shared<UndefinedInstruction>(machInst, false,
326 mnemonic);
327 }
328

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422 "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
423 header_output += DCStore64Declare.subst(msrDCZVAIop);
424 decoder_output += DCStore64Constructor.subst(msrDCZVAIop);
425 exec_output += DCStore64Execute.subst(msrDCZVAIop);
426 exec_output += DCStore64InitiateAcc.subst(msrDCZVAIop);
427 exec_output += Store64CompleteAcc.subst(msrDCZVAIop);
428
429
430
431 buildDataXImmInst("msrSP", '''
432 if (!canWriteAArch64SysReg(
433 (MiscRegIndex) xc->tcBase()->flattenRegId(
434 RegId(MiscRegClass, dest)).index(),
435 Scr64, Cpsr, xc->tcBase())) {
436 return std::make_shared<UndefinedInstruction>(machInst, false,
437 mnemonic);
438 }

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