1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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289 msrMrs64EnabledCheckCode = '''
290 // Check for read/write access right
291 if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) {
292 if (flat_idx == MISCREG_DAIF ||
293 flat_idx == MISCREG_DC_ZVA_Xt ||
294 flat_idx == MISCREG_DC_CVAC_Xt ||
295 flat_idx == MISCREG_DC_CIVAC_Xt
296 )
297 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
298 return new UndefinedInstruction(machInst, false, mnemonic);
299 }
300
301 // Check for traps to supervisor (FP/SIMD regs)
302 if (el <= EL1 && msrMrs64TrapToSup(flat_idx, el, Cpacr64))
303 return new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_SIMD_FP);
304
305 bool is_vfp_neon = false;

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391 }
392 MiscDest_ud = imm;
393 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
394
395 buildDataXImmInst("msrDAIFSet", '''
396 if (!canWriteAArch64SysReg(
397 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
398 Scr64, Cpsr, xc->tcBase())) {
399 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
400 }
401 CPSR cpsr = Cpsr;
402 cpsr.daif = cpsr.daif | imm;
403 Cpsr = cpsr;
404 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
405
406 buildDataXImmInst("msrDAIFClr", '''
407 if (!canWriteAArch64SysReg(
408 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
409 Scr64, Cpsr, xc->tcBase())) {
410 return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
411 }
412 CPSR cpsr = Cpsr;
413 cpsr.daif = cpsr.daif & ~imm;
414 Cpsr = cpsr;
415 ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
416
417 def buildDataXCompInst(mnem, instType, suffix, code):
418 global header_output, decoder_output, exec_output

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