1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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321 )
322 return std::make_shared<UndefinedInstruction>(
323 machInst, 0, EC_TRAPPED_MSR_MRS_64,
324 mnemonic);
325 return std::make_shared<UndefinedInstruction>(machInst, false,
326 mnemonic);
327 }
328
329 fault = this->trap(xc->tcBase(), flat_idx, el, imm);
330 if (fault != NoFault) return fault;
331 '''
332
333 mrsCode = '''
334 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
335 flattenRegId(RegId(MiscRegClass, op1)).index();
336 CPSR cpsr = Cpsr;
337 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
338 %s
339 XDest = MiscOp1_ud;
340 ''' % (msrMrs64EnabledCheckCode % ('Read'),)
341
342 mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
343 mrsCode,
344 ["IsSerializeBefore"])
345 header_output += RegMiscRegOp64Declare.subst(mrsIop)
346 decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
347 exec_output += BasicExecute.subst(mrsIop)
348

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356
357 msrCode = '''
358 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
359 flattenRegId(RegId(MiscRegClass, dest)).index();
360 CPSR cpsr = Cpsr;
361 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
362 %s
363 MiscDest_ud = XOp1;
364 ''' % (msrMrs64EnabledCheckCode % ('Write'),)
365
366 msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
367 msrCode,
368 ["IsSerializeAfter", "IsNonSpeculative"])
369 header_output += MiscRegRegOp64Declare.subst(msrIop)
370 decoder_output += MiscRegRegOp64Constructor.subst(msrIop)
371 exec_output += BasicExecute.subst(msrIop)
372

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379 ''')
380
381 msr_check_code = '''
382 MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
383 flattenRegId(RegId(MiscRegClass, dest)).index();
384 CPSR cpsr = Cpsr;
385 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
386 %s
387 ''' % (msrMrs64EnabledCheckCode % ('Write'),)
388
389
390 msrdczva_ea_code = msr_check_code
391 msrdczva_ea_code += '''
392 Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO |
393 ArmISA::TLB::MustBeOne;
394 EA = XBase;
395 assert(!(Dczid & 0x10));

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