pred.isa (8301:858384f3af1c) pred.isa (8303:5a95f1d2494e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 39 unchanged lines hidden (view full) ---

48 CpsrQ = (Rd < resTemp) ? 1 << 27 : 0;
49 } else {
50 uint16_t _ic, _iv, _iz, _in;
51 _in = (resTemp >> %(negBit)d) & 1;
52 _iz = (resTemp == 0);
53 _iv = %(ivValue)s & 1;
54 _ic = %(icValue)s & 1;
55
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 39 unchanged lines hidden (view full) ---

48 CpsrQ = (Rd < resTemp) ? 1 << 27 : 0;
49 } else {
50 uint16_t _ic, _iv, _iz, _in;
51 _in = (resTemp >> %(negBit)d) & 1;
52 _iz = (resTemp == 0);
53 _iv = %(ivValue)s & 1;
54 _ic = %(icValue)s & 1;
55
56 CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
56 CondCodesNZ = (_in << 1) | (_iz);
57 CondCodesC = _ic;
58 CondCodesV = _iv;
57
58 DPRINTF(Arm, "in = %%d\\n", _in);
59 DPRINTF(Arm, "iz = %%d\\n", _iz);
60 DPRINTF(Arm, "ic = %%d\\n", _ic);
61 DPRINTF(Arm, "iv = %%d\\n", _iv);
62 }
63 '''
64}};
65
66let {{
67 def getCcCode(flagtype):
68 icReg = icImm = iv = ''
69 negBit = 31
70 canOverflow = 'false'
71
72 if flagtype == "none":
59
60 DPRINTF(Arm, "in = %%d\\n", _in);
61 DPRINTF(Arm, "iz = %%d\\n", _iz);
62 DPRINTF(Arm, "ic = %%d\\n", _ic);
63 DPRINTF(Arm, "iv = %%d\\n", _iv);
64 }
65 '''
66}};
67
68let {{
69 def getCcCode(flagtype):
70 icReg = icImm = iv = ''
71 negBit = 31
72 canOverflow = 'false'
73
74 if flagtype == "none":
73 icReg = icImm = 'CondCodesF<29:>'
74 iv = 'CondCodesF<28:>'
75 icReg = icImm = 'CondCodesC'
76 iv = 'CondCodesV'
75 elif flagtype == "llbit":
77 elif flagtype == "llbit":
76 icReg = icImm = 'CondCodesF<29:>'
77 iv = 'CondCodesF<28:>'
78 icReg = icImm = 'CondCodesC'
79 iv = 'CondCodesV'
78 negBit = 63
79 elif flagtype == "overflow":
80 canOverflow = "true"
81 icReg = icImm = iv = '0'
82 elif flagtype == "add":
83 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
84 iv = 'findOverflow(32, resTemp, Rn, op2)'
85 elif flagtype == "sub":
86 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)'
87 iv = 'findOverflow(32, resTemp, Rn, ~op2)'
88 elif flagtype == "rsb":
89 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
90 iv = 'findOverflow(32, resTemp, op2, ~Rn)'
91 else:
80 negBit = 63
81 elif flagtype == "overflow":
82 canOverflow = "true"
83 icReg = icImm = iv = '0'
84 elif flagtype == "add":
85 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
86 iv = 'findOverflow(32, resTemp, Rn, op2)'
87 elif flagtype == "sub":
88 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)'
89 iv = 'findOverflow(32, resTemp, Rn, ~op2)'
90 elif flagtype == "rsb":
91 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
92 iv = 'findOverflow(32, resTemp, op2, ~Rn)'
93 else:
92 icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesF<29:>)'
93 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesF<29:>)'
94 iv = 'CondCodesF<28:>'
94 icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
95 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
96 iv = 'CondCodesV'
95 return (calcCcCode % {"icValue" : icReg,
96 "ivValue" : iv,
97 "negBit" : negBit,
98 "canOverflow" : canOverflow },
99 calcCcCode % {"icValue" : icImm,
100 "ivValue" : iv,
101 "negBit" : negBit,
102 "canOverflow" : canOverflow })
103
104 def getImmCcCode(flagtype):
105 ivValue = icValue = ''
106 negBit = 31
107 canOverflow = 'false'
108 if flagtype == "none":
97 return (calcCcCode % {"icValue" : icReg,
98 "ivValue" : iv,
99 "negBit" : negBit,
100 "canOverflow" : canOverflow },
101 calcCcCode % {"icValue" : icImm,
102 "ivValue" : iv,
103 "negBit" : negBit,
104 "canOverflow" : canOverflow })
105
106 def getImmCcCode(flagtype):
107 ivValue = icValue = ''
108 negBit = 31
109 canOverflow = 'false'
110 if flagtype == "none":
109 icValue = 'CondCodesF<29:>'
110 ivValue = 'CondCodesF<28:>'
111 icValue = 'CondCodesC'
112 ivValue = 'CondCodesV'
111 elif flagtype == "llbit":
113 elif flagtype == "llbit":
112 icValue = 'CondCodesF<29:>'
113 ivValue = 'CondCodesF<28:>'
114 icValue = 'CondCodesC'
115 ivValue = 'CondCodesV'
114 negBit = 63
115 elif flagtype == "overflow":
116 icVaule = ivValue = '0'
117 canOverflow = "true"
118 elif flagtype == "add":
119 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
120 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
121 elif flagtype == "sub":
122 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)'
123 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)'
124 elif flagtype == "rsb":
125 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
126 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
127 elif flagtype == "modImm":
128 icValue = 'rotated_carry'
116 negBit = 63
117 elif flagtype == "overflow":
118 icVaule = ivValue = '0'
119 canOverflow = "true"
120 elif flagtype == "add":
121 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
122 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
123 elif flagtype == "sub":
124 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)'
125 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)'
126 elif flagtype == "rsb":
127 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
128 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
129 elif flagtype == "modImm":
130 icValue = 'rotated_carry'
129 ivValue = 'CondCodesF<28:>'
131 ivValue = 'CondCodesV'
130 else:
132 else:
131 icValue = '(rotate ? rotated_carry:CondCodesF<29:>)'
132 ivValue = 'CondCodesF<28:>'
133 icValue = '(rotate ? rotated_carry:CondCodesC)'
134 ivValue = 'CondCodesV'
133 return calcCcCode % vars()
134}};
135
136def format DataOp(code, flagtype = logic) {{
137 (regCcCode, immCcCode) = getCcCode(flagtype)
138 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
135 return calcCcCode % vars()
136}};
137
138def format DataOp(code, flagtype = logic) {{
139 (regCcCode, immCcCode) = getCcCode(flagtype)
140 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
139 shift, CondCodesF<29:>);
141 shift, CondCodesC);
140 op2 = op2;''' + code
141 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
142 op2 = op2;''' + code
143 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
142 shift, CondCodesF<29:>);
144 shift, CondCodesC);
143 op2 = op2;''' + code
144 regIop = InstObjParams(name, Name, 'PredIntOp',
145 {"code": regCode,
146 "predicate_test": predicateTest})
147 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
148 {"code": immCode,
149 "predicate_test": predicateTest})
150 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',

--- 59 unchanged lines hidden --- 		145 op2 = op2;''' + code
146 regIop = InstObjParams(name, Name, 'PredIntOp',
147 {"code": regCode,
148 "predicate_test": predicateTest})
149 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
150 {"code": immCode,
151 "predicate_test": predicateTest})
152 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',

--- 59 unchanged lines hidden ---