pred.isa (6724:70129fdded75) pred.isa (6741:73d89772f409)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 67 unchanged lines hidden (view full) ---

76def template DataImmDecode {{
77 if (machInst.sField == 0)
78 return new %(class_name)s(machInst);
79 else
80 return new %(class_name)sCc(machInst);
81}};
82
83let {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 67 unchanged lines hidden (view full) ---

76def template DataImmDecode {{
77 if (machInst.sField == 0)
78 return new %(class_name)s(machInst);
79 else
80 return new %(class_name)sCc(machInst);
81}};
82
83let {{
84
85 calcCcCode = '''
86 if (%(canOverflow)s){
87 cprintf("canOverflow: %%d\\n", Rd < resTemp);
88 replaceBits(CondCodes, 27, Rd < resTemp);
89 } else {
90 uint16_t _ic, _iv, _iz, _in;
91 _in = (resTemp >> %(negBit)d) & 1;
92 _iz = (resTemp == 0);
93 _iv = %(ivValue)s & 1;
94 _ic = %(icValue)s & 1;
95
96 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
97 (CondCodes & 0x0FFFFFFF);
84
98
85 calcCcCode = '''
86 uint16_t _ic, _iv, _iz, _in;
87
88 _in = (resTemp >> 31) & 1;
89 _iz = (resTemp == 0);
90 _iv = %(ivValue)s & 1;
91 _ic = %(icValue)s & 1;
92
93 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
94 (CondCodes & 0x0FFFFFFF);
95
96 DPRINTF(Arm, "in = %%d\\n", _in);
97 DPRINTF(Arm, "iz = %%d\\n", _iz);
98 DPRINTF(Arm, "ic = %%d\\n", _ic);
99 DPRINTF(Arm, "iv = %%d\\n", _iv);
99 DPRINTF(Arm, "in = %%d\\n", _in);
100 DPRINTF(Arm, "iz = %%d\\n", _iz);
101 DPRINTF(Arm, "ic = %%d\\n", _ic);
102 DPRINTF(Arm, "iv = %%d\\n", _iv);
103 }
100 '''
104 '''
101
102}};
103
104let {{
105 def getCcCode(flagtype):
106 icReg = icImm = iv = ''
105}};
106
107let {{
108 def getCcCode(flagtype):
109 icReg = icImm = iv = ''
110 negBit = 31
111 canOverflow = 'false'
112
107 if flagtype == "none":
108 icReg = icImm = 'CondCodes<29:>'
109 iv = 'CondCodes<28:>'
113 if flagtype == "none":
114 icReg = icImm = 'CondCodes<29:>'
115 iv = 'CondCodes<28:>'
116 elif flagtype == "llbit":
117 icReg = icImm = 'CondCodes<29:>'
118 iv = 'CondCodes<28:>'
119 negBit = 63
120 elif flagtype == "overflow":
121 canOverflow = "true"
122 icReg = icImm = iv = '0'
110 elif flagtype == "add":
111 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
112 iv = 'findOverflow(32, resTemp, Rn, op2)'
113 elif flagtype == "sub":
114 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)'
115 iv = 'findOverflow(32, resTemp, Rn, ~op2)'
116 elif flagtype == "rsb":
117 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
118 iv = 'findOverflow(32, resTemp, op2, ~Rn)'
119 else:
123 elif flagtype == "add":
124 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
125 iv = 'findOverflow(32, resTemp, Rn, op2)'
126 elif flagtype == "sub":
127 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)'
128 iv = 'findOverflow(32, resTemp, Rn, ~op2)'
129 elif flagtype == "rsb":
130 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
131 iv = 'findOverflow(32, resTemp, op2, ~Rn)'
132 else:
120 icReg = 'shift_carry_rs(Rm, Rs, shift, CondCodes<29:>)'
133 icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodes<29:>)'
121 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodes<29:>)'
122 iv = 'CondCodes<28:>'
134 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodes<29:>)'
135 iv = 'CondCodes<28:>'
123 return (calcCcCode % {"icValue" : icReg, "ivValue" : iv},
124 calcCcCode % {"icValue" : icImm, "ivValue" : iv})
136 return (calcCcCode % {"icValue" : icReg,
137 "ivValue" : iv,
138 "negBit" : negBit,
139 "canOverflow" : canOverflow },
140 calcCcCode % {"icValue" : icImm,
141 "ivValue" : iv,
142 "negBit" : negBit,
143 "canOverflow" : canOverflow })
125
126 def getImmCcCode(flagtype):
127 ivValue = icValue = ''
144
145 def getImmCcCode(flagtype):
146 ivValue = icValue = ''
147 negBit = 31
148 canOverflow = 'false'
128 if flagtype == "none":
129 icValue = 'CondCodes<29:>'
130 ivValue = 'CondCodes<28:>'
149 if flagtype == "none":
150 icValue = 'CondCodes<29:>'
151 ivValue = 'CondCodes<28:>'
152 elif flagtype == "llbit":
153 icValue = 'CondCodes<29:>'
154 ivValue = 'CondCodes<28:>'
155 negBit = 63
156 elif flagtype == "overflow":
157 icVaule = ivValue = '0'
158 canOverflow = "true"
131 elif flagtype == "add":
132 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
133 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
134 elif flagtype == "sub":
135 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)'
136 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)'
137 elif flagtype == "rsb":
138 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
139 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
140 else:
141 icValue = '(rotate ? rotated_carry:CondCodes<29:>)'
142 ivValue = 'CondCodes<28:>'
143 return calcCcCode % vars()
144}};
145
146def format DataOp(code, flagtype = logic) {{
147 (regCcCode, immCcCode) = getCcCode(flagtype)
159 elif flagtype == "add":
160 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
161 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
162 elif flagtype == "sub":
163 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)'
164 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)'
165 elif flagtype == "rsb":
166 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
167 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
168 else:
169 icValue = '(rotate ? rotated_carry:CondCodes<29:>)'
170 ivValue = 'CondCodes<28:>'
171 return calcCcCode % vars()
172}};
173
174def format DataOp(code, flagtype = logic) {{
175 (regCcCode, immCcCode) = getCcCode(flagtype)
148 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs,
149 shift, CondCodes<29:0>);
176 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
177 shift, CondCodes<29:>);
150 op2 = op2;''' + code
151 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
178 op2 = op2;''' + code
179 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
152 shift, CondCodes<29:0>);
180 shift, CondCodes<29:>);
153 op2 = op2;''' + code
154 regIop = InstObjParams(name, Name, 'PredIntOp',
155 {"code": regCode,
156 "predicate_test": predicateTest})
157 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
158 {"code": immCode,
159 "predicate_test": predicateTest})
160 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',

--- 100 unchanged lines hidden --- 		181 op2 = op2;''' + code
182 regIop = InstObjParams(name, Name, 'PredIntOp',
183 {"code": regCode,
184 "predicate_test": predicateTest})
185 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
186 {"code": immCode,
187 "predicate_test": predicateTest})
188 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',

--- 100 unchanged lines hidden ---